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Re: [Qemu-devel] [PATCH] target-mips: gdbstub: Clean up FPU register han
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From: |
Maciej W. Rozycki |
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Subject: |
Re: [Qemu-devel] [PATCH] target-mips: gdbstub: Clean up FPU register handling |
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Date: |
Fri, 5 Dec 2014 18:56:22 +0000 |
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User-agent: |
Alpine 1.10 (DEB 962 2008-03-14) |
On Fri, 5 Dec 2014, Leon Alrae wrote:
> > qemu-mips-gdbstub-cleanup.diff
> > Index: qemu-git-trunk/target-mips/gdbstub.c
> > ===================================================================
> > --- qemu-git-trunk.orig/target-mips/gdbstub.c 2014-11-20
> > 10:44:24.058944521 +0000
> > +++ qemu-git-trunk/target-mips/gdbstub.c 2014-11-20 10:44:28.058940153
> > +0000
[...]
> > @@ -107,6 +100,12 @@ int mips_cpu_gdb_write_register(CPUState
> > case 71:
> > /* FIR is read-only. Ignore writes. */
> > break;
> > + default:
> > + if (env->CP0_Status & (1 << CP0St_FR))
> > + env->active_fpu.fpr[n - 38].d = tmp;
> > + else
> > + env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
>
> Braces are missing here.
Fixed in v2, thanks for your review.
Maciej