Re: [Qemu-devel] [PATCH] ARM64: support access to more performance registers in AA64 mode

[Chengyu Song]

Hello Peter,

Sorry for replying late.

> We're up to rev A.d now; you can get it from
> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0487a.d/index.html
> (if you haven't registered on the ARM website before you'll need
> to fill in a form but it's a fairly painless process.)

Thank you for the information, I have resubmitted the patch according to the 
new revision.

> By implementing the register's behaviour; there's only one
> bit of state we care about since we don't model any
> perf counters except the cycle counter. The overflow bit
> is handled by a set/clear pair of register accessors,
> and we also need to check on reads to see if the
> cycle counter would have overflowed (in which case we
> need to set the bit to 1), using a similar logic to how
> we deal with reads of the cycle counter itself. (A similar
> check also needs to be done when the cycle counter is
> written to or when it is disabled.)

Thank you for the instruction, I have added the support for PMOVSSET.

> Are there any other bits of new-in-v8 perf counter
> functionality we're missing?

Yes. But the rest ones are all related to events:

PMCEID0_EL0, PMCEID1_EL0, PMEVCNTR<n>_EL0, PMEVTYPER<n>_EL0, PMXEVCNTR_EL0

and their corresponding AA32 mappings.

Best,
Chengyu