[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 27/33] target-arm: make MAIR0/1 banked
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 27/33] target-arm: make MAIR0/1 banked |
Date: |
Thu, 11 Dec 2014 12:19:49 +0000 |
From: Greg Bellows <address@hidden>
Added CP register info entries for the ARMv7 MAIR0/1 secure banks.
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 21 ++++++++++++++++++++-
target-arm/helper.c | 12 +++++++++---
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a1fefe4..7ba55f0 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -296,7 +296,26 @@ typedef struct CPUARMState {
uint32_t c9_pmxevtyper; /* perf monitor event type */
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
- uint64_t mair_el1;
+ union { /* Memory attribute redirection */
+ struct {
+#ifdef HOST_WORDS_BIGENDIAN
+ uint64_t _unused_mair_0;
+ uint32_t mair1_ns;
+ uint32_t mair0_ns;
+ uint64_t _unused_mair_1;
+ uint32_t mair1_s;
+ uint32_t mair0_s;
+#else
+ uint64_t _unused_mair_0;
+ uint32_t mair0_ns;
+ uint32_t mair1_ns;
+ uint64_t _unused_mair_1;
+ uint32_t mair0_s;
+ uint32_t mair1_s;
+#endif
+ };
+ uint64_t mair_el[4];
+ };
union { /* vector base address register */
struct {
uint64_t _unused_vbar;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0357f41..96abbed 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -965,20 +965,26 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
*/
{ .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
.resetvalue = 0 },
/* For non-long-descriptor page tables these are PRRR and NMRR;
* regardless they still act as reads-as-written for QEMU.
* The override is necessary because of the overly-broad TLB_LOCKDOWN
* definition.
*/
+ /* MAIR0/1 are defined seperately from their 64-bit counterpart which
+ * allows them to assign the correct fieldoffset based on the endianness
+ * handled in the field definitions.
+ */
{ .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
+ offsetof(CPUARMState, cp15.mair0_ns) },
.resetfn = arm_cp_reset_ignore },
{ .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
.cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
- .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
+ offsetof(CPUARMState, cp15.mair1_ns) },
.resetfn = arm_cp_reset_ignore },
{ .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
--
1.9.1
- [Qemu-devel] [PULL 00/33] target-arm queue, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 33/33] target-arm: Check error conditions on kvm_arm_reset_vcpu, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 32/33] target-arm: Support save/load for 64 bit CPUs, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 30/33] arm_gic_kvm: Tell kernel about number of IRQs, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 27/33] target-arm: make MAIR0/1 banked,
Peter Maydell <=
- [Qemu-devel] [PULL 28/33] hw/arm/realview.c: Fix memory leak in realview_init(), Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 31/33] target-arm/kvm: make reg sync code common between kvm32/64, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 24/33] target-arm: make PAR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 23/33] target-arm: make IFAR/DFAR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 21/33] target-arm: make IFSR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 26/33] target-arm: make c13 cp regs banked (FCSEIDR, ...), Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 29/33] hw/arm/boot: fix uninitialized scalar variable warning reported by coverity, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 17/33] target-arm: make CSSELR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 18/33] target-arm: make TTBR0/1 banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 19/33] target-arm: make TTBCR banked, Peter Maydell, 2014/12/11