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[Qemu-devel] [PULL 07/33] target-arm: add CPREG secure state support
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 07/33] target-arm: add CPREG secure state support |
Date: |
Thu, 11 Dec 2014 12:19:29 +0000 |
From: Fabian Aggeler <address@hidden>
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Also added secure state tracking field and flags. This allows for
identification of the register info secure state.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 36 ++++++++++++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 6881098..dd7d229 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -993,6 +993,21 @@ enum {
ARM_CP_STATE_BOTH = 2,
};
+/* ARM CP register secure state flags. These flags identify security state
+ * attributes for a given CP register entry.
+ * The existence of both or neither secure and non-secure flags indicates that
+ * the register has both a secure and non-secure hash entry. A single one of
+ * these flags causes the register to only be hashed for the specified
+ * security state.
+ * Although definitions may have any combination of the S/NS bits, each
+ * registered entry will only have one to identify whether the entry is secure
+ * or non-secure.
+ */
+enum {
+ ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
+ ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
+};
+
/* Return true if cptype is a valid type field. This is used to try to
* catch errors where the sentinel has been accidentally left off the end
* of a list of registers.
@@ -1127,6 +1142,8 @@ struct ARMCPRegInfo {
int type;
/* Access rights: PL*_[RW] */
int access;
+ /* Security state: ARM_CP_SECSTATE_* bits/values */
+ int secure;
/* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
* this register was defined: can be used to hand data through to the
* register read/write functions, since they are passed the ARMCPRegInfo*.
@@ -1136,12 +1153,27 @@ struct ARMCPRegInfo {
* fieldoffset is non-zero, the reset value of the register.
*/
uint64_t resetvalue;
- /* Offset of the field in CPUARMState for this register. This is not
- * needed if either:
+ /* Offset of the field in CPUARMState for this register.
+ *
+ * This is not needed if either:
* 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
* 2. both readfn and writefn are specified
*/
ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
+
+ /* Offsets of the secure and non-secure fields in CPUARMState for the
+ * register if it is banked. These fields are only used during the static
+ * registration of a register. During hashing the bank associated
+ * with a given security state is copied to fieldoffset which is used from
+ * there on out.
+ *
+ * It is expected that register definitions use either fieldoffset or
+ * bank_fieldoffsets in the definition but not both. It is also expected
+ * that both bank offsets are set when defining a banked register. This
+ * use indicates that a register is banked.
+ */
+ ptrdiff_t bank_fieldoffsets[2];
+
/* Function for making any access checks for this register in addition to
* those specified by the 'access' permissions bits. If NULL, no extra
* checks required. The access check is performed at runtime, not at
--
1.9.1
- [Qemu-devel] [PULL 19/33] target-arm: make TTBCR banked, (continued)
- [Qemu-devel] [PULL 19/33] target-arm: make TTBCR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 16/33] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 22/33] target-arm: make DFSR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 14/33] target-arm: add MVBAR support, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 12/33] target-arm: add NSACR register, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 25/33] target-arm: make VBAR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 15/33] target-arm: add SCTLR_EL3 and make SCTLR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 11/33] target-arm: implement IRQ/FIQ routing to Monitor mode, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 10/33] target-arm: move AArch32 SCR into security reglist, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 09/33] target-arm: insert AArch32 cpregs twice into hashtable, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 07/33] target-arm: add CPREG secure state support,
Peter Maydell <=
- [Qemu-devel] [PULL 06/33] target-arm: add non-secure Translation Block flag, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 05/33] target-arm: add banked register accessors, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 02/33] Add the "-semihosting-config" option., Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 20/33] target-arm: make DACR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 08/33] target-arm: add secure state bit to CPREG hash, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 03/33] target-arm: extend async excp masking, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 13/33] target-arm: add SDER definition, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 01/33] Pass semihosting exit code back to system., Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 04/33] target-arm: add async excp target_el function, Peter Maydell, 2014/12/11
- Re: [Qemu-devel] [PULL 00/33] target-arm queue, Peter Maydell, 2014/12/11