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[Qemu-devel] [PULL 36/47] target-i386: add Ivy Bridge CPU model
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 36/47] target-i386: add Ivy Bridge CPU model |
Date: |
Mon, 15 Dec 2014 17:38:20 +0100 |
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-i386/cpu.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index b2bb9a4..b81ac5c 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1042,6 +1042,38 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
},
{
+ .name = "IvyBridge",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 6,
+ .model = 58,
+ .stepping = 9,
+ .features[FEAT_1_EDX] =
+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+ CPUID_DE | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
+ CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+ CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
+ CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_ERMS,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
+ CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_LAHF_LM,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT,
+ .xlevel = 0x8000000A,
+ .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
+ },
+ {
.name = "Haswell",
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
--
1.8.3.1
- Re: [Qemu-devel] [PULL 27/47] icount: set can_do_io outside TB execution, (continued)
- [Qemu-devel] [PULL 25/47] cpu-exec: fix cpu_exec_nocache, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 28/47] icount: introduce cpu_get_icount_raw, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 29/47] cpu-exec: invalidate nocache translation if they are interrupted, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 30/47] timer: introduce new QEMU_CLOCK_VIRTUAL_RT clock, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 31/47] cpus: make icount warp behave well with respect to stop/cont, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 32/47] i386: do not cross the pages boundaries in replay mode, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 34/47] target-i386: add VME to all CPUs, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 33/47] pc: add 2.3 machine types, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 35/47] target-i386: add f16c and rdrand to Haswell and Broadwell, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 36/47] target-i386: add Ivy Bridge CPU model,
Paolo Bonzini <=
- [Qemu-devel] [PULL 38/47] linuxboot: fix loading old kernels, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 37/47] kvm/apic: fix 2.2->2.1 migration, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 39/47] serial: reset thri_pending on IER writes with THRI=0, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 40/47] serial: clean up THRE/TEMT handling, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 42/47] serial: only resample THR interrupt on rising edge of IER.THRI, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 41/47] serial: update LSR on enabling/disabling FIFOs, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 43/47] sdhci: Set a default frequency clock, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 44/47] sdhci: Remove class "virtual" methods, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 45/47] sdhci: Add "sysbus" to sdhci QOM types and methods, Paolo Bonzini, 2014/12/15
- [Qemu-devel] [PULL 46/47] sdhci: Define SDHCI PCI ids, Paolo Bonzini, 2014/12/15