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[Qemu-devel] [PULL 09/30] target-mips: Fix formatting in `decode_opc'
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 09/30] target-mips: Fix formatting in `decode_opc' |
Date: |
Tue, 16 Dec 2014 19:48:55 +0000 |
From: "Maciej W. Rozycki" <address@hidden>
Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 643214a..a5a5ca4 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -18340,7 +18340,7 @@ static void gen_msa(CPUMIPSState *env, DisasContext
*ctx)
}
-static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
+static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
{
int32_t offset;
int rs, rt, rd, sa;
@@ -18506,7 +18506,8 @@ static void decode_opc (CPUMIPSState *env, DisasContext
*ctx)
save_cpu_state(ctx, 1);
gen_helper_di(t0, cpu_env);
gen_store_gpr(t0, rt);
- /* Stop translation as we may have switched the execution
mode */
+ /* Stop translation as we may have switched
+ the execution mode. */
ctx->bstate = BS_STOP;
break;
case OPC_EI:
@@ -18514,7 +18515,8 @@ static void decode_opc (CPUMIPSState *env, DisasContext
*ctx)
save_cpu_state(ctx, 1);
gen_helper_ei(t0, cpu_env);
gen_store_gpr(t0, rt);
- /* Stop translation as we may have switched the execution
mode */
+ /* Stop translation as we may have switched
+ the execution mode. */
ctx->bstate = BS_STOP;
break;
default: /* Invalid */
@@ -18780,8 +18782,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext
*ctx)
gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa);
break;
default:
- gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
- (imm >> 8) & 0x7);
+ gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f),
+ rt, rd, sa, (imm >> 8) & 0x7);
+
break;
}
} else {
--
2.1.0
- [Qemu-devel] [PULL 00/30] target-mips queue, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 01/30] target-mips: Correct the handling of register #72 on writes, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 02/30] target-mips: Make CP1.FIR read-only here too, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 03/30] target-mips: Add 5KEc and 5KEf MIPS64r2 processors, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 09/30] target-mips: Fix formatting in `decode_opc',
Leon Alrae <=
- [Qemu-devel] [PULL 10/30] target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpers, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 11/30] target-mips: Remove unused `FLOAT_OP' macro, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 13/30] target-mips: Correct MIPS16/microMIPS branch size calculation, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 17/30] target-mips: Output CP0.Config2-5 in the register dump, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 14/30] target-mips: Correct the handling of writes to CP0.Status for MIPSr6, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 15/30] target-mips: Correct the writes to Status and Cause registers via gdbstub, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 12/30] target-mips: Restore the order of helpers, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 16/30] target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 21/30] target-mips: gdbstub: Clean up FPU register handling, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 22/30] target-mips: Also apply the CP0.Status mask to MTTC0, Leon Alrae, 2014/12/16