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[Qemu-devel] [PATCH 1/2] target-arm : update reference manual chapter nu
|
From: |
Chih-Min Chao |
|
Subject: |
[Qemu-devel] [PATCH 1/2] target-arm : update reference manual chapter number |
|
Date: |
Wed, 24 Dec 2014 00:25:02 +0800 |
Update the reference manual version to DDI0487A_c
Instruction set encoding is moved from C3 to C4
Instruction set Description is moved from C5/C6 to C6/C7
Signed-off-by: Chih-Min Chao <address@hidden>
---
target-arm/helper-a64.c | 2 +-
target-arm/translate-a64.c | 228 +++++++++++++++++++++++----------------------
2 files changed, 116 insertions(+), 114 deletions(-)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 81066ca..83ca899 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -27,7 +27,7 @@
#include "qemu/crc32c.h"
#include <zlib.h> /* For crc32 */
-/* C2.4.7 Multiply and divide */
+/* C3.4.7 Multiply and divide */
/* special cases for 0 and LLONG_MIN are mandated by the standard */
uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
{
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 80d2c07..979572a 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1046,11 +1046,11 @@ static inline AArch64DecodeFn *lookup_disas_fn(const
AArch64DecodeTable *table,
/*
* the instruction disassembly implemented here matches
- * the instruction encoding classifications in chapter 3 (C3)
- * of the ARM Architecture Reference Manual (DDI0487A_a)
+ * the instruction encoding classifications in chapter 4 (C4)
+ * of the ARM Architecture Reference Manual (DDI0487A_c)
*/
-/* C3.2.7 Unconditional branch (immediate)
+/* C4.2.7 Unconditional branch (immediate)
* 31 30 26 25 0
* +----+-----------+-------------------------------------+
* | op | 0 0 1 0 1 | imm26 |
@@ -1061,15 +1061,15 @@ static void disas_uncond_b_imm(DisasContext *s,
uint32_t insn)
uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
if (insn & (1 << 31)) {
- /* C5.6.26 BL Branch with link */
+ /* C6.6.26 BL Branch with link */
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
}
- /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
+ /* C6.6.20 B Branch / C6.6.26 BL Branch with link */
gen_goto_tb(s, 0, addr);
}
-/* C3.2.1 Compare & branch (immediate)
+/* C4.2.1 Compare & branch (immediate)
* 31 30 25 24 23 5 4 0
* +----+-------------+----+---------------------+--------+
* | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
@@ -1098,7 +1098,7 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t
insn)
gen_goto_tb(s, 1, addr);
}
-/* C3.2.5 Test & branch (immediate)
+/* C4.2.5 Test & branch (immediate)
* 31 30 25 24 23 19 18 5 4 0
* +----+-------------+----+-------+-------------+------+
* | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
@@ -1127,7 +1127,7 @@ static void disas_test_b_imm(DisasContext *s, uint32_t
insn)
gen_goto_tb(s, 1, addr);
}
-/* C3.2.2 / C5.6.19 Conditional branch (immediate)
+/* C4.2.2 / C6.6.19 Conditional branch (immediate)
* 31 25 24 23 5 4 3 0
* +---------------+----+---------------------+----+------+
* | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
@@ -1158,7 +1158,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t
insn)
}
}
-/* C5.6.68 HINT */
+/* C6.6.68 HINT */
static void handle_hint(DisasContext *s, uint32_t insn,
unsigned int op1, unsigned int op2, unsigned int crm)
{
@@ -1218,7 +1218,7 @@ static void handle_sync(DisasContext *s, uint32_t insn,
}
}
-/* C5.6.130 MSR (immediate) - move immediate to processor state field */
+/* C6.6.130 MSR (immediate) - move immediate to processor state field */
static void handle_msr_i(DisasContext *s, uint32_t insn,
unsigned int op1, unsigned int op2, unsigned int crm)
{
@@ -1292,10 +1292,10 @@ static void gen_set_nzcv(TCGv_i64 tcg_rt)
tcg_temp_free_i32(nzcv);
}
-/* C5.6.129 MRS - move from system register
- * C5.6.131 MSR (register) - move to system register
- * C5.6.204 SYS
- * C5.6.205 SYSL
+/* C6.6.129 MRS - move from system register
+ * C6.6.131 MSR (register) - move to system register
+ * C6.6.204 SYS
+ * C6.6.205 SYSL
* These are all essentially the same insn in 'read' and 'write'
* versions, with varying op0 fields.
*/
@@ -1416,7 +1416,7 @@ static void handle_sys(DisasContext *s, uint32_t insn,
bool isread,
}
}
-/* C3.2.4 System
+/* C4.2.4 System
* 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
* +---------------------+---+-----+-----+-------+-------+-----+------+
* | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
@@ -1439,13 +1439,13 @@ static void disas_system(DisasContext *s, uint32_t insn)
return;
}
switch (crn) {
- case 2: /* C5.6.68 HINT */
+ case 2: /* C6.6.68 HINT */
handle_hint(s, insn, op1, op2, crm);
break;
case 3: /* CLREX, DSB, DMB, ISB */
handle_sync(s, insn, op1, op2, crm);
break;
- case 4: /* C5.6.130 MSR (immediate) */
+ case 4: /* C6.6.130 MSR (immediate) */
handle_msr_i(s, insn, op1, op2, crm);
break;
default:
@@ -1457,7 +1457,7 @@ static void disas_system(DisasContext *s, uint32_t insn)
handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
}
-/* C3.2.3 Exception generation
+/* C4.2.3 Exception generation
*
* 31 24 23 21 20 5 4 2 1 0
* +-----------------+-----+------------------------+-----+----+
@@ -1543,7 +1543,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
}
}
-/* C3.2.7 Unconditional branch (register)
+/* C4.2.7 Unconditional branch (register)
* 31 25 24 21 20 16 15 10 9 5 4 0
* +---------------+-------+-------+-------+------+-------+
* | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
@@ -1596,7 +1596,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t
insn)
s->is_jmp = DISAS_JUMP;
}
-/* C3.2 Branches, exception generating and system instructions */
+/* C4.2 Branches, exception generating and system instructions */
static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 25, 7)) {
@@ -1745,7 +1745,7 @@ static void gen_store_exclusive(DisasContext *s, int rd,
int rt, int rt2,
}
#endif
-/* C3.3.6 Load/store exclusive
+/* C4.3.6 Load/store exclusive
*
* 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
* +-----+-------------+----+---+----+------+----+-------+------+------+
@@ -1816,7 +1816,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t
insn)
}
/*
- * C3.3.5 Load register (literal)
+ * C4.3.5 Load register (literal)
*
* 31 30 29 27 26 25 24 23 5 4 0
* +-----+-------+---+-----+-------------------+-------+
@@ -1868,15 +1868,17 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
}
/*
- * C5.6.80 LDNP (Load Pair - non-temporal hint)
- * C5.6.81 LDP (Load Pair - non vector)
- * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
- * C5.6.176 STNP (Store Pair - non-temporal hint)
- * C5.6.177 STP (Store Pair - non vector)
- * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
- * C6.3.165 LDP (Load Pair of SIMD&FP)
- * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
- * C6.3.284 STP (Store Pair of SIMD&FP)
+ * C4.3.7 Load/store no-allocate pair (offset)
+ * C6.6.80 LDNP (Load Pair - non-temporal hint)
+ * C6.6.176 STNP (Store Pair - non-temporal hint)
+ * C7.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
+ * C7.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
+ * C4.3.14 Load/store register pair (offset)
+ * C6.6.81 LDP (Load Pair - non vector)
+ * C6.6.82 LDPSW (Load Pair Signed Word - non vector)
+ * C6.6.177 STP (Store Pair - non vector)
+ * C7.3.165 LDP (Load Pair of SIMD&FP)
+ * C7.3.284 STP (Store Pair of SIMD&FP)
*
* 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
* +-----+-------+---+---+-------+---+-----------------------------+
@@ -2013,9 +2015,9 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
}
/*
- * C3.3.8 Load/store (immediate post-indexed)
- * C3.3.9 Load/store (immediate pre-indexed)
- * C3.3.12 Load/store (unscaled immediate)
+ * C4.3.8 Load/store (immediate post-indexed)
+ * C4.3.9 Load/store (immediate pre-indexed)
+ * C4.3.12 Load/store (unscaled immediate)
*
* 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
* +----+-------+---+-----+-----+---+--------+-----+------+------+
@@ -2127,7 +2129,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t
insn)
}
/*
- * C3.3.10 Load/store (register offset)
+ * C4.3.10 Load/store (register offset)
*
* 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
* +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
@@ -2220,7 +2222,7 @@ static void disas_ldst_reg_roffset(DisasContext *s,
uint32_t insn)
}
/*
- * C3.3.13 Load/store (unsigned immediate)
+ * C4.3.13 Load/store (unsigned immediate)
*
* 31 30 29 27 26 25 24 23 22 21 10 9 5
* +----+-------+---+-----+-----+------------+-------+------+
@@ -2323,14 +2325,14 @@ static void disas_ldst_reg(DisasContext *s, uint32_t
insn)
}
}
-/* C3.3.1 AdvSIMD load/store multiple structures
+/* C4.3.1 AdvSIMD load/store multiple structures
*
* 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
* +---+---+---------------+---+-------------+--------+------+------+------+
* | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
* +---+---+---------------+---+-------------+--------+------+------+------+
*
- * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
+ * C4.3.2 AdvSIMD load/store multiple structures (post-indexed)
*
* 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---------------+---+---+---------+--------+------+------+------+
@@ -2455,14 +2457,14 @@ static void disas_ldst_multiple_struct(DisasContext *s,
uint32_t insn)
tcg_temp_free_i64(tcg_addr);
}
-/* C3.3.3 AdvSIMD load/store single structure
+/* C4.3.3 AdvSIMD load/store single structure
*
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
* | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
*
- * C3.3.4 AdvSIMD load/store single structure (post-indexed)
+ * C4.3.4 AdvSIMD load/store single structure (post-indexed)
*
* 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
* +---+---+---------------+-----+-----------+-----+---+------+------+------+
@@ -2605,7 +2607,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
tcg_temp_free_i64(tcg_addr);
}
-/* C3.3 Loads and stores */
+/* C4.3 Loads and stores */
static void disas_ldst(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 24, 6)) {
@@ -2635,7 +2637,7 @@ static void disas_ldst(DisasContext *s, uint32_t insn)
}
}
-/* C3.4.6 PC-rel. addressing
+/* C4.4.6 PC-rel. addressing
* 31 30 29 28 24 23 5 4 0
* +----+-------+-----------+-------------------+------+
* | op | immlo | 1 0 0 0 0 | immhi | Rd |
@@ -2663,7 +2665,7 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t
insn)
}
/*
- * C3.4.1 Add/subtract (immediate)
+ * C4.4.1 Add/subtract (immediate)
*
* 31 30 29 28 24 23 22 21 10 9 5 4 0
* +--+--+--+-----------+-----+-------------+-----+-----+
@@ -2810,7 +2812,7 @@ static bool logic_imm_decode_wmask(uint64_t *result,
unsigned int immn,
return true;
}
-/* C3.4.4 Logical (immediate)
+/* C4.4.4 Logical (immediate)
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
* +----+-----+-------------+---+------+------+------+------+
* | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
@@ -2883,7 +2885,7 @@ static void disas_logic_imm(DisasContext *s, uint32_t
insn)
}
/*
- * C3.4.5 Move wide (immediate)
+ * C4.4.5 Move wide (immediate)
*
* 31 30 29 28 23 22 21 20 5 4 0
* +--+-----+-------------+-----+----------------+------+
@@ -2935,7 +2937,7 @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
}
}
-/* C3.4.2 Bitfield
+/* C4.4.2 Bitfield
* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
* +----+-----+-------------+---+------+------+------+------+
* | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
@@ -2993,7 +2995,7 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
}
}
-/* C3.4.3 Extract
+/* C4.4.3 Extract
* 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
* +----+------+-------------+---+----+------+--------+------+------+
* | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
@@ -3044,7 +3046,7 @@ static void disas_extract(DisasContext *s, uint32_t insn)
}
}
-/* C3.4 Data processing - immediate */
+/* C4.4 Data processing - immediate */
static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 23, 6)) {
@@ -3138,7 +3140,7 @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int
sf,
}
}
-/* C3.5.10 Logical (shifted register)
+/* C4.5.10 Logical (shifted register)
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +----+-----+-----------+-------+---+------+--------+------+------+
* | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
@@ -3229,7 +3231,7 @@ static void disas_logic_reg(DisasContext *s, uint32_t
insn)
}
/*
- * C3.5.1 Add/subtract (extended register)
+ * C4.5.1 Add/subtract (extended register)
*
* 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
* +--+--+--+-----------+-----+--+-------+------+------+----+----+
@@ -3302,7 +3304,7 @@ static void disas_add_sub_ext_reg(DisasContext *s,
uint32_t insn)
}
/*
- * C3.5.2 Add/subtract (shifted register)
+ * C4.5.2 Add/subtract (shifted register)
*
* 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
* +--+--+--+-----------+-----+--+-------+---------+------+------+
@@ -3365,7 +3367,7 @@ static void disas_add_sub_reg(DisasContext *s, uint32_t
insn)
tcg_temp_free_i64(tcg_result);
}
-/* C3.5.9 Data-processing (3 source)
+/* C4.5.9 Data-processing (3 source)
31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
+--+------+-----------+------+------+----+------+------+------+
@@ -3464,7 +3466,7 @@ static void disas_data_proc_3src(DisasContext *s,
uint32_t insn)
tcg_temp_free_i64(tcg_tmp);
}
-/* C3.5.3 - Add/subtract (with carry)
+/* C4.5.3 - Add/subtract (with carry)
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
* +--+--+--+------------------------+------+---------+------+-----+
* |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
@@ -3506,7 +3508,7 @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
}
}
-/* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
+/* C4.5.4 - C4.5.5 Conditional compare (immediate / register)
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
* |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
@@ -3569,7 +3571,7 @@ static void disas_cc(DisasContext *s, uint32_t insn)
}
}
-/* C3.5.6 Conditional select
+/* C4.5.6 Conditional select
* 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
* +----+----+---+-----------------+------+------+-----+------+------+
* | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
@@ -3692,7 +3694,7 @@ static void handle_rbit(DisasContext *s, unsigned int sf,
}
}
-/* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
+/* C6.6.149 REV with sf==1, opcode==3 ("REV64") */
static void handle_rev64(DisasContext *s, unsigned int sf,
unsigned int rn, unsigned int rd)
{
@@ -3703,8 +3705,8 @@ static void handle_rev64(DisasContext *s, unsigned int sf,
tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
}
-/* C5.6.149 REV with sf==0, opcode==2
- * C5.6.151 REV32 (sf==1, opcode==2)
+/* C6.6.149 REV with sf==0, opcode==2
+ * C6.6.151 REV32 (sf==1, opcode==2)
*/
static void handle_rev32(DisasContext *s, unsigned int sf,
unsigned int rn, unsigned int rd)
@@ -3729,7 +3731,7 @@ static void handle_rev32(DisasContext *s, unsigned int sf,
}
}
-/* C5.6.150 REV16 (opcode==1) */
+/* C6.6.150 REV16 (opcode==1) */
static void handle_rev16(DisasContext *s, unsigned int sf,
unsigned int rn, unsigned int rd)
{
@@ -3759,7 +3761,7 @@ static void handle_rev16(DisasContext *s, unsigned int sf,
tcg_temp_free_i64(tcg_tmp);
}
-/* C3.5.7 Data-processing (1 source)
+/* C4.5.7 Data-processing (1 source)
* 31 30 29 28 21 20 16 15 10 9 5 4 0
* +----+---+---+-----------------+---------+--------+------+------+
* | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
@@ -3828,7 +3830,7 @@ static void handle_div(DisasContext *s, bool is_signed,
unsigned int sf,
}
}
-/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
+/* C6.6.115 LSLV, C6.6.118 LSRV, C6.6.17 ASRV, C6.6.154 RORV */
static void handle_shift_reg(DisasContext *s,
enum a64_shift_type shift_type, unsigned int sf,
unsigned int rm, unsigned int rn, unsigned int rd)
@@ -3890,7 +3892,7 @@ static void handle_crc32(DisasContext *s,
tcg_temp_free_i32(tcg_bytes);
}
-/* C3.5.8 Data-processing (2 source)
+/* C4.5.8 Data-processing (2 source)
* 31 30 29 28 21 20 16 15 10 9 5 4 0
* +----+---+---+-----------------+------+--------+------+------+
* | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
@@ -3949,7 +3951,7 @@ static void disas_data_proc_2src(DisasContext *s,
uint32_t insn)
}
}
-/* C3.5 Data processing - register */
+/* C4.5 Data processing - register */
static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 24, 5)) {
@@ -4043,7 +4045,7 @@ static void handle_fp_compare(DisasContext *s, bool
is_double,
tcg_temp_free_i64(tcg_flags);
}
-/* C3.6.22 Floating point compare
+/* C4.6.22 Floating point compare
* 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
* +---+---+---+-----------+------+---+------+-----+---------+------+-------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
@@ -4073,7 +4075,7 @@ static void disas_fp_compare(DisasContext *s, uint32_t
insn)
handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
}
-/* C3.6.23 Floating point conditional compare
+/* C4.6.23 Floating point conditional compare
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
* +---+---+---+-----------+------+---+------+------+-----+------+----+------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
@@ -4135,7 +4137,7 @@ static void gen_mov_fp2fp(DisasContext *s, int type, int
dst, int src)
}
}
-/* C3.6.24 Floating point conditional select
+/* C4.6.24 Floating point conditional select
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+------+-----+------+------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
@@ -4179,7 +4181,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
}
}
-/* C3.6.25 Floating-point data-processing (1 source) - single precision */
+/* C4.6.25 Floating-point data-processing (1 source) - single precision */
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
{
TCGv_ptr fpst;
@@ -4235,7 +4237,7 @@ static void handle_fp_1src_single(DisasContext *s, int
opcode, int rd, int rn)
tcg_temp_free_i32(tcg_res);
}
-/* C3.6.25 Floating-point data-processing (1 source) - double precision */
+/* C4.6.25 Floating-point data-processing (1 source) - double precision */
static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
{
TCGv_ptr fpst;
@@ -4357,7 +4359,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
}
}
-/* C3.6.25 Floating point data-processing (1 source)
+/* C4.6.25 Floating point data-processing (1 source)
* 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
* +---+---+---+-----------+------+---+--------+-----------+------+------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
@@ -4415,7 +4417,7 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
}
}
-/* C3.6.26 Floating-point data-processing (2 source) - single precision */
+/* C4.6.26 Floating-point data-processing (2 source) - single precision */
static void handle_fp_2src_single(DisasContext *s, int opcode,
int rd, int rn, int rm)
{
@@ -4468,7 +4470,7 @@ static void handle_fp_2src_single(DisasContext *s, int
opcode,
tcg_temp_free_i32(tcg_res);
}
-/* C3.6.26 Floating-point data-processing (2 source) - double precision */
+/* C4.6.26 Floating-point data-processing (2 source) - double precision */
static void handle_fp_2src_double(DisasContext *s, int opcode,
int rd, int rn, int rm)
{
@@ -4521,7 +4523,7 @@ static void handle_fp_2src_double(DisasContext *s, int
opcode,
tcg_temp_free_i64(tcg_res);
}
-/* C3.6.26 Floating point data-processing (2 source)
+/* C4.6.26 Floating point data-processing (2 source)
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
@@ -4558,7 +4560,7 @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
}
}
-/* C3.6.27 Floating-point data-processing (3 source) - single precision */
+/* C4.6.27 Floating-point data-processing (3 source) - single precision */
static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
int rd, int rn, int rm, int ra)
{
@@ -4596,7 +4598,7 @@ static void handle_fp_3src_single(DisasContext *s, bool
o0, bool o1,
tcg_temp_free_i32(tcg_res);
}
-/* C3.6.27 Floating-point data-processing (3 source) - double precision */
+/* C4.6.27 Floating-point data-processing (3 source) - double precision */
static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
int rd, int rn, int rm, int ra)
{
@@ -4634,7 +4636,7 @@ static void handle_fp_3src_double(DisasContext *s, bool
o0, bool o1,
tcg_temp_free_i64(tcg_res);
}
-/* C3.6.27 Floating point data-processing (3 source)
+/* C4.6.27 Floating point data-processing (3 source)
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
* +---+---+---+-----------+------+----+------+----+------+------+------+
* | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
@@ -4668,7 +4670,7 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
}
}
-/* C3.6.28 Floating point immediate
+/* C4.6.28 Floating point immediate
* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
* +---+---+---+-----------+------+---+------------+-------+------+------+
* | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
@@ -4839,7 +4841,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int
rn, int opcode,
tcg_temp_free_i32(tcg_shift);
}
-/* C3.6.29 Floating point <-> fixed point conversions
+/* C4.6.29 Floating point <-> fixed point conversions
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
* +----+---+---+-----------+------+---+-------+--------+-------+------+------+
* | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
@@ -4939,7 +4941,7 @@ static void handle_fmov(DisasContext *s, int rd, int rn,
int type, bool itof)
}
}
-/* C3.6.30 Floating point <-> integer conversions
+/* C4.6.30 Floating point <-> integer conversions
* 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
* +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
* | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
@@ -5074,7 +5076,7 @@ static void do_ext64(DisasContext *s, TCGv_i64 tcg_left,
TCGv_i64 tcg_right,
tcg_temp_free_i64(tcg_tmp);
}
-/* C3.6.1 EXT
+/* C4.6.1 EXT
* 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
* +---+---+-------------+-----+---+------+---+------+---+------+------+
* | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
@@ -5147,7 +5149,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_resh);
}
-/* C3.6.2 TBL/TBX
+/* C4.6.2 TBL/TBX
* 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
* +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
* | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
@@ -5215,7 +5217,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_resh);
}
-/* C3.6.3 ZIP/UZP/TRN
+/* C4.6.3 ZIP/UZP/TRN
* 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
* +---+---+-------------+------+---+------+---+------------------+------+
* | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
@@ -5327,7 +5329,7 @@ static void do_minmaxop(DisasContext *s, TCGv_i32
tcg_elt1, TCGv_i32 tcg_elt2,
}
}
-/* C3.6.4 AdvSIMD across lanes
+/* C4.6.4 AdvSIMD across lanes
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
* | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
@@ -5494,7 +5496,7 @@ static void disas_simd_across_lanes(DisasContext *s,
uint32_t insn)
tcg_temp_free_i64(tcg_res);
}
-/* C6.3.31 DUP (Element, Vector)
+/* C7.3.31 DUP (Element, Vector)
*
* 31 30 29 21 20 16 15 10 9 5 4 0
* +---+---+-------------------+--------+-------------+------+------+
@@ -5537,7 +5539,7 @@ static void handle_simd_dupe(DisasContext *s, int is_q,
int rd, int rn,
tcg_temp_free_i64(tmp);
}
-/* C6.3.31 DUP (element, scalar)
+/* C7.3.31 DUP (element, scalar)
* 31 21 20 16 15 10 9 5 4 0
* +-----------------------+--------+-------------+------+------+
* | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
@@ -5570,7 +5572,7 @@ static void handle_simd_dupes(DisasContext *s, int rd,
int rn,
tcg_temp_free_i64(tmp);
}
-/* C6.3.32 DUP (General)
+/* C7.3.32 DUP (General)
*
* 31 30 29 21 20 16 15 10 9 5 4 0
* +---+---+-------------------+--------+-------------+------+------+
@@ -5604,7 +5606,7 @@ static void handle_simd_dupg(DisasContext *s, int is_q,
int rd, int rn,
}
}
-/* C6.3.150 INS (Element)
+/* C7.3.150 INS (Element)
*
* 31 21 20 16 15 14 11 10 9 5 4 0
* +-----------------------+--------+------------+---+------+------+
@@ -5642,7 +5644,7 @@ static void handle_simd_inse(DisasContext *s, int rd, int
rn,
}
-/* C6.3.151 INS (General)
+/* C7.3.151 INS (General)
*
* 31 21 20 16 15 10 9 5 4 0
* +-----------------------+--------+-------------+------+------+
@@ -5671,8 +5673,8 @@ static void handle_simd_insg(DisasContext *s, int rd, int
rn, int imm5)
}
/*
- * C6.3.321 UMOV (General)
- * C6.3.237 SMOV (General)
+ * C7.3.321 UMOV (General)
+ * C7.3.237 SMOV (General)
*
* 31 30 29 21 20 16 15 12 10 9 5 4 0
* +---+---+-------------------+--------+-------------+------+------+
@@ -5717,7 +5719,7 @@ static void handle_simd_umov_smov(DisasContext *s, int
is_q, int is_signed,
}
}
-/* C3.6.5 AdvSIMD copy
+/* C4.6.5 AdvSIMD copy
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
* +---+---+----+-----------------+------+---+------+---+------+------+
* | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
@@ -5769,7 +5771,7 @@ static void disas_simd_copy(DisasContext *s, uint32_t
insn)
}
}
-/* C3.6.6 AdvSIMD modified immediate
+/* C4.6.6 AdvSIMD modified immediate
* 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
* +---+---+----+---------------------+-----+-------+----+---+-------+------+
* | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
@@ -5902,7 +5904,7 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t
insn)
tcg_temp_free_i64(tcg_imm);
}
-/* C3.6.7 AdvSIMD scalar copy
+/* C4.6.7 AdvSIMD scalar copy
* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
* +-----+----+-----------------+------+---+------+---+------+------+
* | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
@@ -5925,7 +5927,7 @@ static void disas_simd_scalar_copy(DisasContext *s,
uint32_t insn)
handle_simd_dupes(s, rd, rn, imm5);
}
-/* C3.6.8 AdvSIMD scalar pairwise
+/* C4.6.8 AdvSIMD scalar pairwise
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +-----+---+-----------+------+-----------+--------+-----+------+------+
* | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
@@ -6651,7 +6653,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s,
bool is_scalar,
tcg_temp_free_i32(tcg_rmode);
}
-/* C3.6.9 AdvSIMD scalar shift by immediate
+/* C4.6.9 AdvSIMD scalar shift by immediate
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
* +-----+---+-------------+------+------+--------+---+------+------+
* | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
@@ -6726,7 +6728,7 @@ static void disas_simd_scalar_shift_imm(DisasContext *s,
uint32_t insn)
}
}
-/* C3.6.10 AdvSIMD scalar three different
+/* C4.6.10 AdvSIMD scalar three different
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +-----+---+-----------+------+---+------+--------+-----+------+------+
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
@@ -7113,7 +7115,7 @@ static void handle_3same_float(DisasContext *s, int size,
int elements,
}
}
-/* C3.6.11 AdvSIMD scalar three same
+/* C4.6.11 AdvSIMD scalar three same
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
* +-----+---+-----------+------+---+------+--------+---+------+------+
* | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
@@ -7784,7 +7786,7 @@ static void handle_2misc_satacc(DisasContext *s, bool
is_scalar, bool is_u,
}
}
-/* C3.6.12 AdvSIMD scalar two reg misc
+/* C4.6.12 AdvSIMD scalar two reg misc
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +-----+---+-----------+------+-----------+--------+-----+------+------+
* | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
@@ -8212,7 +8214,7 @@ static void handle_vec_simd_shrn(DisasContext *s, bool
is_q,
}
-/* C3.6.14 AdvSIMD shift by immediate
+/* C4.6.14 AdvSIMD shift by immediate
* 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
* +---+---+---+-------------+------+------+--------+---+------+------+
* | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
@@ -8637,7 +8639,7 @@ static void handle_pmull_64(DisasContext *s, int is_q,
int rd, int rn, int rm)
tcg_temp_free_i64(tcg_res);
}
-/* C3.6.15 AdvSIMD three different
+/* C4.6.15 AdvSIMD three different
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
@@ -8739,7 +8741,7 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
}
}
-/* Logic op (opcode == 3) subgroup of C3.6.16. */
+/* Logic op (opcode == 3) subgroup of C4.6.16. */
static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
@@ -8841,7 +8843,7 @@ static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1,
TCGv_i32 op2)
tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2);
}
-/* Pairwise op subgroup of C3.6.16.
+/* Pairwise op subgroup of C4.6.16.
*
* This is called directly or via the handle_3same_float for float pairwise
* operations where the opcode and size are calculated differently.
@@ -8998,7 +9000,7 @@ static void handle_simd_3same_pair(DisasContext *s, int
is_q, int u, int opcode,
}
}
-/* Floating point op subgroup of C3.6.16. */
+/* Floating point op subgroup of C4.6.16. */
static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
{
/* For floating point ops, the U, size[1] and opcode bits
@@ -9067,7 +9069,7 @@ static void disas_simd_3same_float(DisasContext *s,
uint32_t insn)
}
}
-/* Integer op subgroup of C3.6.16. */
+/* Integer op subgroup of C4.6.16. */
static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
{
int is_q = extract32(insn, 30, 1);
@@ -9374,7 +9376,7 @@ static void disas_simd_3same_int(DisasContext *s,
uint32_t insn)
}
}
-/* C3.6.16 AdvSIMD three same
+/* C4.6.16 AdvSIMD three same
* 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+--------+---+------+------+
* | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
@@ -9643,7 +9645,7 @@ static void handle_shll(DisasContext *s, bool is_q, int
size, int rn, int rd)
}
}
-/* C3.6.17 AdvSIMD two reg misc
+/* C4.6.17 AdvSIMD two reg misc
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
* | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
@@ -10155,12 +10157,12 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
}
}
-/* C3.6.13 AdvSIMD scalar x indexed element
+/* C4.6.13 AdvSIMD scalar x indexed element
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
* | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
- * C3.6.18 AdvSIMD vector x indexed element
+ * C4.6.18 AdvSIMD vector x indexed element
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
* | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
@@ -10610,7 +10612,7 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
}
}
-/* C3.6.19 Crypto AES
+/* C4.6.19 Crypto AES
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
* +-----------------+------+-----------+--------+-----+------+------+
* | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
@@ -10669,7 +10671,7 @@ static void disas_crypto_aes(DisasContext *s, uint32_t
insn)
tcg_temp_free_i32(tcg_decrypt);
}
-/* C3.6.20 Crypto three-reg SHA
+/* C4.6.20 Crypto three-reg SHA
* 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
* +-----------------+------+---+------+---+--------+-----+------+------+
* | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
@@ -10737,7 +10739,7 @@ static void disas_crypto_three_reg_sha(DisasContext *s,
uint32_t insn)
tcg_temp_free_i32(tcg_rm_regno);
}
-/* C3.6.21 Crypto two-reg SHA
+/* C4.6.21 Crypto two-reg SHA
* 31 24 23 22 21 17 16 12 11 10 9 5 4 0
* +-----------------+------+-----------+--------+-----+------+------+
* | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
@@ -10790,7 +10792,7 @@ static void disas_crypto_two_reg_sha(DisasContext *s,
uint32_t insn)
tcg_temp_free_i32(tcg_rn_regno);
}
-/* C3.6 Data processing - SIMD, inc Crypto
+/* C4.6 Data processing - SIMD, inc Crypto
*
* As the decode gets a little complex we are using a table based
* approach for this part of the decode.
@@ -10836,7 +10838,7 @@ static void disas_data_proc_simd(DisasContext *s,
uint32_t insn)
}
}
-/* C3.6 Data processing - SIMD and floating point */
+/* C4.6 Data processing - SIMD and floating point */
static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
{
if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) {
@@ -10847,7 +10849,7 @@ static void disas_data_proc_simd_fp(DisasContext *s,
uint32_t insn)
}
}
-/* C3.1 A64 instruction index by encoding */
+/* C4.1 A64 instruction index by encoding */
static void disas_a64_insn(CPUARMState *env, DisasContext *s)
{
uint32_t insn;
--
2.1.1
- [Qemu-devel] [PATCH 1/2] target-arm : update reference manual chapter number,
Chih-Min Chao <=