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[Qemu-devel] [PULL 20/37] target-ppc: Introduce Instruction Type for Tra
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 20/37] target-ppc: Introduce Instruction Type for Transactional Memory |
Date: |
Wed, 7 Jan 2015 16:20:31 +0100 |
From: Tom Musta <address@hidden>
Add a category (PPC2_TM) for the Transactional Memory instructions
introduced in Power ISA 2.07.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/cpu.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 068fcb2..3510083 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2010,6 +2010,8 @@ enum {
PPC2_ISA207S = 0x0000000000008000ULL,
/* Double precision floating point conversion for signed integer 64 */
PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
+ /* Transactional Memory (ISA 2.07, Book II) */
+ PPC2_TM = 0x0000000000020000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
@@ -2017,7 +2019,7 @@ enum {
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
- PPC2_FP_CVT_S64)
+ PPC2_FP_CVT_S64 | PPC2_TM)
};
/*****************************************************************************/
--
1.8.1.4
- [Qemu-devel] [PULL 02/37] PPC: e500: Move CCSR and MMIO space to upper end of address space, (continued)
- [Qemu-devel] [PULL 02/37] PPC: e500: Move CCSR and MMIO space to upper end of address space, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 22/37] target-ppc: Introduce tm_enabled Bit to CPU State, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 05/37] target-ppc: Load/Store Vector Element Storage Alignment, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 08/37] target-ppc: mffs. Should Set CR1 from FPSCR Bits, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 13/37] spapr: Fix stale HTAB during live migration (KVM), Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 16/37] device-tree: fix memory leak, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 27/37] target-ppc: Introduce tcheck, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 23/37] target-ppc: Power8 Supports Transactional Memory, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 06/37] target-ppc: VXSQRT Should Not Be Set for NaNs, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 14/37] spapr: Fix integer overflow during migration (TCG), Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 20/37] target-ppc: Introduce Instruction Type for Transactional Memory,
Alexander Graf <=
- [Qemu-devel] [PULL 04/37] PPC: e500 pci host: Add support for ATMUs, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 31/37] target-ppc: Cast ssize_t to size_t before printing with %zx, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 30/37] target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLY, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 10/37] target-ppc: Eliminate set_fprf Argument From gen_compute_fprf, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 17/37] ppc: do not use get_clock_realtime(), Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 12/37] target-ppc: explicitly save page table headers in big endian, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 21/37] target-ppc: Introduce Feature Flag for Transactional Memory, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 07/37] target-ppc: Fix Floating Point Move Instructions That Set CR1, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 01/37] PPC: e500: Move CCSR definition to params, Alexander Graf, 2015/01/07
- [Qemu-devel] [PULL 29/37] PPC: e500: Fix GPIO controller interrupt number, Alexander Graf, 2015/01/07