Re: [Qemu-devel] [PATCH 2/2] m48t59: add mem_base value to m48t59_init_isa()

[Paolo Bonzini]

On 19/01/2015 17:17, Artyom Tarasenko wrote:
> On Mon, Jan 19, 2015 at 4:31 PM, Paolo Bonzini <address@hidden> wrote:
>>
>>
>> On 19/01/2015 16:22, Artyom Tarasenko wrote:
>>>>>>>
>>>>>>> On physical machines it's EBus, which is pretty much like 8-bit ISA.
>>>>>>> So, I think modelling it as ISA is closer to to the reality.
>>>>>>> But out of curiosity, would it be possible to have a sysbus device
>>>>>>> somewhere in a middle of PCI space? [...]
>>>>>
>>>>> Why would you want to use a SysBusDevice in the first place?
>>> Ask Paolo. :-) For me it's only important to have a MMIO device in the
>>> proper address range.
>>
>> The reason I asked is simply because ISA devices never do MMIO (apart
>> for the VGA window).
> 
> You mean in the QEMU world? At least physical SCSI and Ethernet
> adapters had a MMIO space for the onboard ROM.

Uh right, ROMs count as MMIO too.

>>>>> I previously discussed with Mark that it should be an EBusDevice, not an
>>>>> ISADevice or SysBusDevice.
>>> Interesting. I can't find this discussion in the list archive. Do you 
>>> suggest to
>>> create EBusDevices for all ISA devices (serial, parallel, keyboard,
>>> floppy) used in sun4u, or only for m48t59?
>>> What would be the advantage of using EBusDevice over ISADevice?
>>
>> Is there a description of EBus and the sun4u memory map somewhere?
> 
> I could find only sparse pieces. "Uniprocessor System Controller
> User's Manual" (805-0170.pdf) has some brief description, it's also
> mentioned in the STP2223BGA  and STP2200ABGA data sheets.
> 
>> Is there an "EBus bridge" PCI device similar to the PCI-to-ISA bridge?
> 
> As physical devices there are integrated SBus-to-EBus and PCI-to-EBus bridges.
> 
> But actually I may have been wrong about NVRAM always sitting on the
> EBus: looking at the page 28 of "UltraSPARC™-IIi User's Manual"
> (805-0087.pdf), I see that NVRAM, Serial and other controllers reside
> in a "PC compatible SuperIO" chip which sits on a PCI bus.

That's an ISA bridge basically.  I understand a little more of how this
is supposed to work now, but I think it makes little sense to add this
patch without the corresponding user.

Paolo