Re: [Qemu-devel] [PATCH V2 1/4] target-arm: Fix RVBAR_EL1 register encoding

[Peter Maydell]

On 23 January 2015 at 16:17, Greg Bellows <address@hidden> wrote:
> Fix the RVBAR_EL1 CP register opc2 encoding from 2 to 1
>
> Signed-off-by: Greg Bellows <address@hidden>
> ---
>  target-arm/helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 1a5e067..c9b1c08 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3055,7 +3055,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>          };
>          ARMCPRegInfo rvbar = {
>              .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
> -            .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
> +            .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
>              .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
>          };
>          define_one_arm_cp_reg(cpu, &rvbar);
> --

Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM