[Qemu-devel] [PATCH v2 0/4] TriCore add instructions of RR1, RR2, RRPW and RRR opcode format

[Bastian Koppelmann]

Hi,

this is a rather short patchset, that only implements instructions of four
formats. There will be another patchset, which has a few bugfixes.

Cheers,
Bastian

v1 -> v2:
    - Add 3 helper functions (gen_mul_q, gen_mul_q_16, gen_mulr_q) to
      remove repetition.
    - gen_mul_q now uses 64 arithmetic instead of emulating it.
    - MUL_Q now uses arithmetic shift, instead of normal shift + sign extend 
for arg
      extraction.
    - optimize OPC2_32_RRPW_EXTR by using only two shifts, instead of four.
    - OPC1_32_RRPW_DEXTR now has r1 == r2 as a special case.

Bastian Koppelmann (4):
  target-tricore: target-tricore: Add instructions of RR1 opcode format,
    that have 0x93 as first opcode
  target-tricore: Add instructions of RR2 opcode format
  target-tricore: Add instructions of RRPW opcode format
  target-tricore: Add instructions of RRR opcode format

 target-tricore/helper.h          |   8 +
 target-tricore/op_helper.c       | 160 ++++++++++++++
 target-tricore/translate.c       | 439 +++++++++++++++++++++++++++++++++++++++
 target-tricore/tricore-opcodes.h |   2 +-
 4 files changed, 608 insertions(+), 1 deletion(-)

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2.2.2