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[Qemu-devel] [PULL v2 8/9] target-tricore: Add instructions of RRPW opco
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL v2 8/9] target-tricore: Add instructions of RRPW opcode format |
Date: |
Tue, 27 Jan 2015 12:09:24 +0000 |
Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-tricore/translate.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index ea0a2fc..8943a39 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -4991,6 +4991,57 @@ static void decode_rr2_mul(CPUTriCoreState *env,
DisasContext *ctx)
}
}
+/* RRPW format */
+static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
+{
+ uint32_t op2;
+ int r1, r2, r3;
+ int32_t pos, width;
+
+ op2 = MASK_OP_RRPW_OP2(ctx->opcode);
+ r1 = MASK_OP_RRPW_S1(ctx->opcode);
+ r2 = MASK_OP_RRPW_S2(ctx->opcode);
+ r3 = MASK_OP_RRPW_D(ctx->opcode);
+ pos = MASK_OP_RRPW_POS(ctx->opcode);
+ width = MASK_OP_RRPW_WIDTH(ctx->opcode);
+
+ switch (op2) {
+ case OPC2_32_RRPW_EXTR:
+ if (pos + width <= 31) {
+ /* optimize special cases */
+ if ((pos == 0) && (width == 8)) {
+ tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ } else if ((pos == 0) && (width == 16)) {
+ tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ } else {
+ tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos -
width);
+ tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
+ }
+ }
+ break;
+ case OPC2_32_RRPW_EXTR_U:
+ if (width == 0) {
+ tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
+ } else {
+ tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
+ tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
+ }
+ break;
+ case OPC2_32_RRPW_IMASK:
+ if (pos + width <= 31) {
+ tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
+ tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
+ }
+ break;
+ case OPC2_32_RRPW_INSERT:
+ if (pos + width <= 31) {
+ tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ width, pos);
+ }
+ break;
+ }
+}
+
static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
{
int op1;
@@ -5255,6 +5306,25 @@ static void decode_32Bit_opc(CPUTriCoreState *env,
DisasContext *ctx)
case OPCM_32_RR2_MUL:
decode_rr2_mul(env, ctx);
break;
+/* RRPW format */
+ case OPCM_32_RRPW_EXTRACT_INSERT:
+ decode_rrpw_extract_insert(env, ctx);
+ break;
+ case OPC1_32_RRPW_DEXTR:
+ r1 = MASK_OP_RRPW_S1(ctx->opcode);
+ r2 = MASK_OP_RRPW_S2(ctx->opcode);
+ r3 = MASK_OP_RRPW_D(ctx->opcode);
+ const16 = MASK_OP_RRPW_POS(ctx->opcode);
+ if (r1 == r2) {
+ tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
+ } else {
+ temp = tcg_temp_new();
+ tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], const16);
+ tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 32 - const16);
+ tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
+ tcg_temp_free(temp);
+ }
+ break;
}
}
--
2.2.2
- [Qemu-devel] [PULL v2 0/9] tricore patches, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 2/9] target-tricore: Several translator and cpu model fixes, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 3/9] target-tricore: calculate av bits before saturation, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 4/9] target-tricore: Fix bugs found by coverity, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 1/9] target-tricore: Add missing ULL suffix on 64 bit constant, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 5/9] target-tricore: split up suov32 into suov32_pos and suov32_neg, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 8/9] target-tricore: Add instructions of RRPW opcode format,
Bastian Koppelmann <=
- [Qemu-devel] [PULL v2 7/9] target-tricore: Add instructions of RR2 opcode format, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 9/9] target-tricore: Add instructions of RRR opcode format, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 6/9] target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode, Bastian Koppelmann, 2015/01/27
- Re: [Qemu-devel] [PULL v2 0/9] tricore patches, Peter Maydell, 2015/01/27