Re: [Qemu-devel] [PATCH] FMULX should flushes operators to zero when FZ is set.

[Xiangyu Hu]

If RISU sets random FPSCR (FZ bit) values, I think such cases would be covered; it 

doesn’t look like such a corner case.

Maybe I can include some focus tests on this scenario if RISU failed to generate this pattern?

Thanks

- xiangyu

On 28 Jan, 2015, at 11:57 pm, Peter Maydell <address@hidden> wrote:

On 28 January 2015 at 15:54, Alex Bennée <address@hidden> wrote:

Do we have test cases that trip up here? It would be nice to include
them in our testing as the random nature of RISU has obviously failed to
trip up on this instruction.

Risu would probably catch this if we generated and ran test cases
which set the FPSCR bits to something other than the default.
(At least the 32-bit risugen lets you do this; I forget whether
we wired up that bit in the 64-bit support code.)

-- PMM