Re: [Qemu-devel] [PATCH v3 4/4] target-arm: Add AArch32 guest support to KVM64

[Peter Maydell]

On 27 January 2015 at 23:58, Greg Bellows <address@hidden> wrote:
> Add 32-bit to/from 64-bit register synchronization on register gets and puts.
> Set EL1_32BIT feature flag passed to KVM
>
> Signed-off-by: Greg Bellows <address@hidden>
>
> ---
>
> v2 -> v3
> - Conditionalize sync of 32-bit and 64-bit registers
> ---
>  target-arm/kvm64.c | 33 +++++++++++++++++++++++++++++----
>  1 file changed, 29 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
> index ba16821..924b423 100644
> --- a/target-arm/kvm64.c
> +++ b/target-arm/kvm64.c
> @@ -81,8 +81,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
>      int ret;
>      ARMCPU *cpu = ARM_CPU(cs);
>
> -    if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
> -        !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> +    if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
>          fprintf(stderr, "KVM is not supported for this guest CPU type\n");

This change will let you try to run with KVM enabled and
-cpu cortex-a15 on a 64-bit host kernel, which is not right.
Worse, because the kernel's KVM_ARM_TARGET_CORTEX_A15 and
KVM_ARM_TARGET_AEM_V8 are the same value the VCPU init ioctl
may succeed but instantiate the wrong kind of CPU.
It probably needs to turn into a check whether cpu is a
subclass of TYPE_AARCH64_CPU.

>          return -EINVAL;
>      }
> @@ -96,6 +95,9 @@ int kvm_arch_init_vcpu(CPUState *cs)
>          cpu->psci_version = 2;
>          cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
>      }
> +    if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> +        cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
> +    }
>
>      /* Do KVM_ARM_VCPU_INIT ioctl */
>      ret = kvm_arm_vcpu_init(cs);
> @@ -133,6 +135,13 @@ int kvm_arch_put_registers(CPUState *cs, int level)
>      ARMCPU *cpu = ARM_CPU(cs);
>      CPUARMState *env = &cpu->env;
>
> +    /* If we are in AArch32 mode then we need to sync the AArch64 regs with 
> the
> +     * AArch32 regs before pushing them out 64-bit KVM.
> +     */
> +    if (!is_a64(env)) {
> +        aarch64_sync_32_to_64(env);
> +    }
> +
>      for (i = 0; i < 31; i++) {
>          reg.id = AARCH64_CORE_REG(regs.regs[i]);
>          reg.addr = (uintptr_t) &env->xregs[i];
> @@ -162,7 +171,11 @@ int kvm_arch_put_registers(CPUState *cs, int level)
>      }
>
>      /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
> -    val = pstate_read(env);
> +    if (is_a64(env)) {
> +        val = pstate_read(env);
> +    } else {
> +        val = cpsr_read(env);
> +    }
>      reg.id = AARCH64_CORE_REG(regs.pstate);
>      reg.addr = (uintptr_t) &val;
>      ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
> @@ -219,6 +232,13 @@ int kvm_arch_get_registers(CPUState *cs)
>          }
>      }
>
> +    /* If we are in AArch32 mode then we need to sync the AArch32 regs with 
> the
> +     * incoming AArch64 regs received from 64-bit KVM.
> +     */
> +    if (!is_a64(env)) {
> +        aarch64_sync_64_to_32(env);
> +    }

This is happening too early, for two reasons:
 (1) this is_a64() call needs to operate on the state we read from
 the kernel, and we don't read the PSTATE from the kernel til later
 (2) aarch64_sync_64_to_32() reads env->pc, which again we haven't
 read from the kernel yet

> +
>      reg.id = AARCH64_CORE_REG(regs.sp);
>      reg.addr = (uintptr_t) &env->sp_el[0];
>      ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
> @@ -239,7 +259,12 @@ int kvm_arch_get_registers(CPUState *cs)
>      if (ret) {
>          return ret;
>      }
> -    pstate_write(env, val);
> +    if (is_a64(env)) {

The value currently in env->aarch64 is junk left over from the last
time execution stopped. What you need to do first is
   env->aarch64 = ((val & PSTATE_nRW) == 0);

(compare target-arm/machine.c:get_cpsr()).

> +        pstate_write(env, val);
> +    } else {
> +        env->uncached_cpsr = val & CPSR_M;
> +        cpsr_write(env, val, 0xffffffff);
> +    }
>
>      /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
>       * QEMU side we keep the current SP in xregs[31] as well.

thanks
-- PMM