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[Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx us
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT |
Date: |
Thu, 5 Feb 2015 14:02:54 +0000 |
The LDT/STT (load/store unprivileged) instruction decode was using
the wrong MMU index value. This meant that instead of these insns
being "always access as if user-mode regardless of current privilege"
they were "always access as if kernel-mode regardless of current
privilege". This went unnoticed because AArch64 Linux doesn't use
these instructions.
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
---
I'm not counting this as a security issue because I'm assuming
nobody treats TCG guests as a security boundary (certainly I
would not recommend doing so...)
---
target-arm/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 80d2359..dac2f63 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2107,7 +2107,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t
insn)
}
} else {
TCGv_i64 tcg_rt = cpu_reg(s, rt);
- int memidx = is_unpriv ? 1 : get_mem_index(s);
+ int memidx = is_unpriv ? MMU_USER_IDX : get_mem_index(s);
if (is_store) {
do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx);
--
1.9.1
- [Qemu-devel] [PULL 27/28] target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64, (continued)
- [Qemu-devel] [PULL 27/28] target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 25/28] disas/arm-a64.cc: Tell libvixl correct code addresses, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 20/28] target-arm: Pass mmu_idx to get_phys_addr(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 23/28] target-arm: Fix brace style in reindented code, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 12/28] hw/arm/virt: explain device-to-transport mapping in create_virtio_devices(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 22/28] target-arm: Reindent ancient page-table-walk code, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 17/28] target-arm: Use correct mmu_idx for unprivileged loads and stores, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 11/28] target-arm: check that LSB <= MSB in BFI instruction, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 08/28] target-arm: Add checks that cpreg raw accesses are handled, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 18/28] target-arm: Don't define any MMU_MODE*_SUFFIXes, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT,
Peter Maydell <=
- [Qemu-devel] [PULL 19/28] target-arm: Split AArch64 cases out of ats_write(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register definition, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 03/28] target-arm: Fix RVBAR_EL1 register encoding, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 21/28] target-arm: Use mmu_idx in get_phys_addr(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 09/28] Fix FMULX not squashing denormalized inputs when FZ is set., Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 14/28] target-arm: Make arm_current_el() return sensible values for M profile, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 16/28] target-arm: Define correct mmu_idx values and pass them in TB flags, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 04/28] target-arm: Add extended RVBAR support, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 13/28] cpu_ldst.h: Allow NB_MMU_MODES to be 7, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 10/28] target-arm: Squash input denormals in FRECPS and FRSQRTS, Peter Maydell, 2015/02/05