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[Qemu-devel] [PULL 10/28] target-arm: Squash input denormals in FRECPS a
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/28] target-arm: Squash input denormals in FRECPS and FRSQRTS |
Date: |
Thu, 5 Feb 2015 14:02:49 +0000 |
The helper functions for FRECPS and FRSQRTS have special case
handling that includes checks for zero inputs, so squash input
denormals if necessary before those checks. This fixes incorrect
output when the FPCR DZ bit is set to enable squashing of input
denormals.
Signed-off-by: Peter Maydell <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
---
target-arm/helper-a64.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index ebd9247..8aa40e9 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -229,6 +229,9 @@ float32 HELPER(recpsf_f32)(float32 a, float32 b, void
*fpstp)
{
float_status *fpst = fpstp;
+ a = float32_squash_input_denormal(a, fpst);
+ b = float32_squash_input_denormal(b, fpst);
+
a = float32_chs(a);
if ((float32_is_infinity(a) && float32_is_zero(b)) ||
(float32_is_infinity(b) && float32_is_zero(a))) {
@@ -241,6 +244,9 @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void
*fpstp)
{
float_status *fpst = fpstp;
+ a = float64_squash_input_denormal(a, fpst);
+ b = float64_squash_input_denormal(b, fpst);
+
a = float64_chs(a);
if ((float64_is_infinity(a) && float64_is_zero(b)) ||
(float64_is_infinity(b) && float64_is_zero(a))) {
@@ -253,6 +259,9 @@ float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void
*fpstp)
{
float_status *fpst = fpstp;
+ a = float32_squash_input_denormal(a, fpst);
+ b = float32_squash_input_denormal(b, fpst);
+
a = float32_chs(a);
if ((float32_is_infinity(a) && float32_is_zero(b)) ||
(float32_is_infinity(b) && float32_is_zero(a))) {
@@ -265,6 +274,9 @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void
*fpstp)
{
float_status *fpst = fpstp;
+ a = float64_squash_input_denormal(a, fpst);
+ b = float64_squash_input_denormal(b, fpst);
+
a = float64_chs(a);
if ((float64_is_infinity(a) && float64_is_zero(b)) ||
(float64_is_infinity(b) && float64_is_zero(a))) {
--
1.9.1
- [Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT, (continued)
- [Qemu-devel] [PULL 15/28] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 19/28] target-arm: Split AArch64 cases out of ats_write(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 06/28] target-arm: Add missing SP_ELx register definition, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 03/28] target-arm: Fix RVBAR_EL1 register encoding, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 21/28] target-arm: Use mmu_idx in get_phys_addr(), Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 09/28] Fix FMULX not squashing denormalized inputs when FZ is set., Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 14/28] target-arm: Make arm_current_el() return sensible values for M profile, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 16/28] target-arm: Define correct mmu_idx values and pass them in TB flags, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 04/28] target-arm: Add extended RVBAR support, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 13/28] cpu_ldst.h: Allow NB_MMU_MODES to be 7, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 10/28] target-arm: Squash input denormals in FRECPS and FRSQRTS,
Peter Maydell <=
- [Qemu-devel] [PULL 05/28] target-arm: Change reset to highest available EL, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 02/28] target_arm: Parameterise the irq lines for armv7m_init, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 24/28] disas/libvixl: Update to upstream VIXL 1.7, Peter Maydell, 2015/02/05
- [Qemu-devel] [PULL 07/28] target-arm: Split NO_MIGRATE into ALIAS and NO_RAW, Peter Maydell, 2015/02/05
- Re: [Qemu-devel] [PULL 00/28] target-arm queue, Peter Maydell, 2015/02/05