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Re: [Qemu-devel] [PATCH v4 3/4] target-arm: Add 32/64-bit register sync


From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH v4 3/4] target-arm: Add 32/64-bit register sync
Date: Wed, 11 Feb 2015 06:20:50 +0000

On 11 February 2015 at 06:08, Greg Bellows <address@hidden> wrote:
>
>
> On Tue, Feb 10, 2015 at 10:13 PM, Peter Maydell <address@hidden>
> wrote:
>>
>> On 10 February 2015 at 10:50, Greg Bellows <address@hidden>
>> wrote:
>> > +void aarch64_sync_64_to_32(CPUARMState *env)
>> > +{
>> > +    int i;
>> > +
>> > +    for (i = 0; i < 15; i++) {
>> > +        env->regs[i] = env->xregs[i];
>> > +    }
>> > +}
>>
>> This is inside CONFIG_USER_ONLY, right? Is it called at all?
>> If so, when?
>
>
> The exception_return helper calls the function so I had to either add a
> USER_CONFIG version of wrap the call in exception return with
> CONFIG_USER_ONLY.  I chose the former, but either would work.  As you would
> already know, the exception_return helper is likely not getting called in a
> USER_ONLY build.

Right, so make it just g_assert_not_reached().

>>
>> > +     * The AArch32 registers 8-12 are only sync'd when we are in USR or
>> > FIQ
>> > +     * mode as they are the only modes where AArch64 registers map to
>> > these
>> > +     * registers.  In all other cases, the respective USR and FIQ banks
>> > are
>> > +     * sync'd.
>> > +     * The AArch32 registers 13 & 14 are sync'd depending on the
>> > execution mode
>> > +     * we are in.  If we are not in a given mode, the bank
>> > corresponding to the
>> > +     * AArch64 register is sync'd.
>> > +     */
>> > +    if (mode == ARM_CPU_MODE_USR) {
>> > +        for (i = 8; i < 15; i++) {
>> > +            env->regs[i] = env->xregs[i];
>> > +        }
>>
>> Something is wrong here, because we don't seem to be writing
>> anything to env->regs[8..15] if mode is neither USR nor FIQ.
>>
> I wrestled with this myself.  As I understand it, nothing maps to
> regs[8..15] unless we are in USR or FIQ, which I covered.  This based on the
> ARM ARM xregs[8:15] are defined to specifically map to USR,   Outside of the
> these modes, what should be copied to regs[8..15]?

There is always *something* that is the architecturally defined
state for all the AArch32 registers. Otherwise a 64-bit hypervisor
would be unable to interrupt and restart a 32-bit guest.
(And all the registers r0..r15 exist in all AArch32 modes;
the question is just whether they're banked registers or
shared with some other mode).

All modes other than FIQ use the USR registers for r0..r12.
(See the v8 ARM ARM fig G1-3, and note the footnote about the
meaning of empty cells in the table.) r13 is the appropriate
sp for the mode (noting that system mode shares with usr),
and r14 ditto (but system and hyp share with usr).

-- PMM



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