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[Qemu-devel] [PATCH 08/11] target-arm: Use setcond and movcond for csel
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 08/11] target-arm: Use setcond and movcond for csel |
Date: |
Thu, 19 Feb 2015 13:14:26 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 60 +++++++++++++++++++---------------------------
1 file changed, 24 insertions(+), 36 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index d139b2d..7549267 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3703,7 +3703,8 @@ static void disas_cc(DisasContext *s, uint32_t insn)
static void disas_cond_select(DisasContext *s, uint32_t insn)
{
unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
- TCGv_i64 tcg_rd, tcg_src;
+ TCGv_i64 tcg_rd, zero;
+ DisasCompare c;
if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
/* S == 1 or op2<1> == 1 */
@@ -3718,48 +3719,35 @@ static void disas_cond_select(DisasContext *s, uint32_t
insn)
rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5);
- if (rd == 31) {
- /* silly no-op write; until we use movcond we must special-case
- * this to avoid a dead temporary across basic blocks.
- */
- return;
- }
-
tcg_rd = cpu_reg(s, rd);
- if (cond >= 0x0e) { /* condition "always" */
- tcg_src = read_cpu_reg(s, rn, sf);
- tcg_gen_mov_i64(tcg_rd, tcg_src);
- } else {
- /* OPTME: we could use movcond here, at the cost of duplicating
- * a lot of the arm_gen_test_cc() logic.
- */
- TCGLabel *label_match = gen_new_label();
- TCGLabel *label_continue = gen_new_label();
-
- arm_gen_test_cc(cond, label_match);
- /* nomatch: */
- tcg_src = cpu_reg(s, rm);
+ arm_test_cc(&c, cond);
+ zero = tcg_const_i64(0);
+ if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
+ /* CSET & CSETM. */
+ tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero);
+ if (else_inv) {
+ tcg_gen_neg_i64(tcg_rd, tcg_rd);
+ }
+ } else {
+ TCGv_i64 t_true = cpu_reg(s, rn);
+ TCGv_i64 t_false = read_cpu_reg(s, rm, 1);
if (else_inv && else_inc) {
- tcg_gen_neg_i64(tcg_rd, tcg_src);
+ tcg_gen_neg_i64(t_false, t_false);
} else if (else_inv) {
- tcg_gen_not_i64(tcg_rd, tcg_src);
+ tcg_gen_not_i64(t_false, t_false);
} else if (else_inc) {
- tcg_gen_addi_i64(tcg_rd, tcg_src, 1);
- } else {
- tcg_gen_mov_i64(tcg_rd, tcg_src);
- }
- if (!sf) {
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+ tcg_gen_addi_i64(t_false, t_false, 1);
}
- tcg_gen_br(label_continue);
- /* match: */
- gen_set_label(label_match);
- tcg_src = read_cpu_reg(s, rn, sf);
- tcg_gen_mov_i64(tcg_rd, tcg_src);
- /* continue: */
- gen_set_label(label_continue);
+ tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
+ }
+
+ tcg_temp_free_i64(zero);
+ arm_free_cc(&c);
+
+ if (!sf) {
+ tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
}
--
2.1.0
- [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 03/11] target-arm: Handle always condition codes within arm_test_cc, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 04/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 01/11] target-arm: Introduce DisasCompare, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 05/11] target-arm: Recognize UXTB, UXTH, LSR, LSL, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 02/11] target-arm: Extend NZCF to 64 bits, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 08/11] target-arm: Use setcond and movcond for csel,
Richard Henderson <=
- [Qemu-devel] [PATCH 09/11] target-arm: Implement ccmp branchless, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 06/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 07/11] target-arm: Recognize ROR, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 10/11] target-arm: Implement fccmp branchless, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 11/11] target-arm: Implement fcsel with movcond, Richard Henderson, 2015/02/19
- Re: [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments, Peter Maydell, 2015/02/19