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[Qemu-devel] [PULL v3 10/26] pc: acpi: drop manual hole punching for GPE
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v3 10/26] pc: acpi: drop manual hole punching for GPE0 resources |
Date: |
Mon, 2 Mar 2015 11:59:08 +0100 |
From: Igor Mammedov <address@hidden>
Drops manual hole punching in PCI0._CRS on PIIX4 machine type
for GPE0 resources. Resources will be consumed by Device(GPE0)
that is attached to PCI namespace.
There is GPE device with HID ACPI0006 since ACPI2.0
that should be used for this purpose but none of Windows
versions support it and show it as "unknown device",
so reserve resource in old fashioned way with PNP0A06
device to make windows happy and actually reserve resources.
Along with last hole _CRS layout of PIIX4 machine becomes
the same as Q35 one, so merge them together and use the same
_CRS for both machine types.
Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/i386/acpi-build.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 0de261a..2700154 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -876,21 +876,10 @@ build_ssdt(GArray *table_data, GArray *linker,
aml_word_io(aml_min_fixed, aml_max_fixed,
aml_pos_decode, aml_entire_range,
0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
- if (ich9_lpc_find()) { /* Q35 */
- aml_append(crs,
- aml_word_io(aml_min_fixed, aml_max_fixed,
- aml_pos_decode, aml_entire_range,
- 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
- } else { /* piix4 */
- aml_append(crs,
- aml_word_io(aml_min_fixed, aml_max_fixed,
- aml_pos_decode, aml_entire_range,
- 0x0000, 0x0D00, 0xAFDF, 0x0000, 0xA2E0));
- aml_append(crs,
- aml_word_io(aml_min_fixed, aml_max_fixed,
- aml_pos_decode, aml_entire_range,
- 0x0000, 0xAFE4, 0xFFFF, 0x0000, 0x501C));
- }
+ aml_append(crs,
+ aml_word_io(aml_min_fixed, aml_max_fixed,
+ aml_pos_decode, aml_entire_range,
+ 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
aml_append(crs,
aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
aml_cacheable, aml_ReadWrite,
@@ -909,6 +898,19 @@ build_ssdt(GArray *table_data, GArray *linker,
}
aml_append(scope, aml_name_decl("_CRS", crs));
+ /* reserve GPE0 block resources */
+ dev = aml_device("GPE0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
+ aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
+ /* device present, functioning, decoding, not shown in UI */
+ aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
+ );
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+
/* reserve PCIHP resources */
if (pm->pcihp_io_len) {
dev = aml_device("PHPR");
--
MST
- [Qemu-devel] [PULL v3 00/26] pci, pc, virtio fixes and cleanups, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 01/26] balloon: call qdev_alias_all_properties for proxy dev in balloon class init, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 02/26] tpm: Extend sts register to 32 bit, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 04/26] tpm: Support for XFIFO register, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 03/26] tpm: Allow 32 & 16 bit accesses to the registers, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 05/26] tpm: Support for TIS selftest done flag, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 06/26] tpm: Support for capability flags of TIS 1.3, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 09/26] pc: acpi: drop manual hole punching for CPU hotplug resources, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 07/26] pc: acpi-build: create PCI0._CRS dynamically, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 08/26] pc: acpi: drop manual hole punching for PCI hotplug resources, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 10/26] pc: acpi: drop manual hole punching for GPE0 resources,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v3 12/26] acpi: add acpi_irq_no_flags() term, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 11/26] pc: acpi-build: drop remaining ssdt_misc template, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 13/26] pc: export applesmc IO port/len, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 14/26] pc: acpi-build: drop template patching and create Device(SMC) dynamically, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 15/26] tests: ACPI test blobs update due to PCI0._CRS changes, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 16/26] tests: bios-tables-test: add support for testing bridges, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 17/26] tests: add ACPI blobs for qemu with bridge cases, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 18/26] pc: acpi-build: simplify PCI bus tree generation, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 19/26] tests: ACPI: update pc/SSDT.bridge due to new alg of PCI tree creation, Michael S. Tsirkin, 2015/03/02
- [Qemu-devel] [PULL v3 20/26] pc: acpi-build: drop template patching and create PCI bus tree dynamically, Michael S. Tsirkin, 2015/03/02