On Thu, Feb 26, 2015 at 4:31 PM, John Snow <address@hidden
<mailto:address@hidden>> wrote:
(Please don't top-post on qemu-devel: gmail is kind of awful about
this, but if you expand the conversation while in-reply, you can
edit beneath the quote instead of above.)
On 02/26/2015 04:31 PM, Jordan Hargrave wrote:
The problem is the FIS registers have stale data.
SeaBIOS initialization leaves the registers:
PORT_FIS_ADDR = 0x7fae0000
PORT_FIS_ADDR_HI = 0x0
My OS initializes DMAR page tables and then enables the IOMMU
translation.
Then OS initializes AHCI driver. Writes VIRTUAL DMA to FIS
registers.
eg. FIS DMA address is 0x10000 (maps to some hardware physical
address
via iommu)
The OS writes 0x00 PORT_FIS_ADDR_HI -> qemu calls map_page (0x00
<< 32)
| 0x7fae0000... 0x7fae0000 is stale, and is not in the IOMMU
page map.
Causes a non-recoverable IOMMU fault.
OK, I see.
We can probably fix this by delaying the map and having it map
on-demand before first access, setting a dirty flag if the registers
have changed since last use.
It might be an AHCI spec violation to change this register once the
FIS Receive Engine is active, too, so it might not be too hard of a
change; perhaps we can just map the FIS Receive Buffer once the FRE
is started.
Did you want to send a patch, or should I?
--js
I'm not as familiar with qemu internals yet to figure out how to map the
memory on demand. I switched order of FIS initialization in my OS
driver for the time being. The same problem was happening with the
PORT_ADDR_LST/PORT_ADDR_LST_HI register initialization pwas well.