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[Qemu-devel] [PATCH target-arm v2 05/15] arm: xlnx-zynqmp: Connect CPU T
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v2 05/15] arm: xlnx-zynqmp: Connect CPU Timers to GIC |
Date: |
Mon, 2 Mar 2015 16:28:51 -0800 |
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index b9bf8db..dc84192 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -19,9 +19,17 @@
#define GIC_NUM_SPI_INTR 128
+#define ARM_PHYS_TIMER_PPI 30
+#define ARM_VIRT_TIMER_PPI 27
+
#define GIC_DIST_ADDR 0xf9010000
#define GIC_CPU_ADDR 0xf9020000
+static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
+{
+ return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index;
+}
+
static void xlnx_zynqmp_init(Object *obj)
{
XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
@@ -59,11 +67,19 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, GIC_CPU_ADDR);
for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
+ qemu_irq irq;
+
object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
ERR_PROP_CHECK_RETURN(err, errp);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
+ arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
+ arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
}
}
--
2.3.0.1.g27a12f1
- [Qemu-devel] [PATCH target-arm v2 00/15] Next Generation Xilinx Zynq SoC, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 05/15] arm: xlnx-zynqmp: Connect CPU Timers to GIC,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v2 04/15] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 07/15] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 13/15] arm: xilinx-ep108: Add external RAM, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 12/15] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 03/15] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 15/15] arm: xlnx-zynqmp: Add PSCI setup, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 02/15] target-arm: cpu64: Add support for cortex-a53, Peter Crosthwaite, 2015/03/02