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[Qemu-devel] [PATCH target-arm v2 04/15] arm: xlnx-zynqmp: Add GIC
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v2 04/15] arm: xlnx-zynqmp: Add GIC |
Date: |
Mon, 2 Mar 2015 16:28:51 -0800 |
And connect IRQ outputs to the CPUs.
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
hw/arm/xlnx-zynqmp.c | 19 +++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 2 ++
2 files changed, 21 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 1b58d65..b9bf8db 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -17,6 +17,11 @@
#include "hw/arm/xlnx-zynqmp.h"
+#define GIC_NUM_SPI_INTR 128
+
+#define GIC_DIST_ADDR 0xf9010000
+#define GIC_CPU_ADDR 0xf9020000
+
static void xlnx_zynqmp_init(Object *obj)
{
XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
@@ -27,6 +32,9 @@ static void xlnx_zynqmp_init(Object *obj)
"cortex-a53-" TYPE_ARM_CPU);
object_property_add_child(obj, "cpu", OBJECT(&s->cpu[i]),
&error_abort);
}
+
+ object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
+ qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
}
#define ERR_PROP_CHECK_RETURN(err, errp) do { \
@@ -42,9 +50,20 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
uint8_t i;
Error *err = NULL;
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
+ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS);
+ object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
+ ERR_PROP_CHECK_RETURN(err, errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, GIC_DIST_ADDR);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, GIC_CPU_ADDR);
+
for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
ERR_PROP_CHECK_RETURN(err, errp);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
+ qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
}
}
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index d6b3b92..d29c7de 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -2,6 +2,7 @@
#include "qemu-common.h"
#include "hw/arm/arm.h"
+#include "hw/intc/arm_gic.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
@@ -15,6 +16,7 @@ typedef struct XlnxZynqMPState {
/*< public >*/
ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
+ GICState gic;
} XlnxZynqMPState;
#define XLNX_ZYNQMP_H_
--
2.3.0.1.g27a12f1
- [Qemu-devel] [PATCH target-arm v2 00/15] Next Generation Xilinx Zynq SoC, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 05/15] arm: xlnx-zynqmp: Connect CPU Timers to GIC, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 04/15] arm: xlnx-zynqmp: Add GIC,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v2 07/15] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 13/15] arm: xilinx-ep108: Add external RAM, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 12/15] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 03/15] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 15/15] arm: xlnx-zynqmp: Add PSCI setup, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 02/15] target-arm: cpu64: Add support for cortex-a53, Peter Crosthwaite, 2015/03/02
- [Qemu-devel] [PATCH target-arm v2 01/15] target-arm: cpu64: Factor out ARM cortex init, Peter Crosthwaite, 2015/03/02