Re: [Qemu-devel] [PATCH 02/11] target-arm: Extend NZCF to 64 bits

[Richard Henderson]

On 03/10/2015 09:08 AM, Peter Maydell wrote:
> On 19 February 2015 at 21:14, Richard Henderson <address@hidden> wrote:
>> The resulting aarch64 translation is a bit cleaner.
>> Sign-extending from 32-bits is simpler than having
>> to use setcond to narrow from 64-bits.
>>
>> Signed-off-by: Richard Henderson <address@hidden>
> 
> 
>> @@ -4545,6 +4548,9 @@ void aarch64_sync_64_to_32(CPUARMState *env)
>>          env->regs[i] = env->xregs[i];
>>      }
>>
>> +    /* Need to compress Z into the low bits.  */
>> +    env->ZF = (env->ZF != 0);
>> +
> 
> I really don't like this. Having state with a different format
> in 32-bit and 64-bit modes is asking for trouble -- the bits
> we already have to convert are already awkward enough.
> 
> I'd much rather we stuck with a format where env->ZF is
> the same regardless of register width, as we have now.

Err.. it is the same format, from the viewpoint of outside TCG generated code.

>From the viewpoint inside TCG generated code, for AArch32, ZF is only 32-bits
wide.  For AArch64, ZF is 64-bits wide.  So when we transition from AArch64 to
AArch32, we must make sure that if ZF != 0, then ZF <= 0xffffffff.

It's a similar concept for NF and VF, except there I can arrange for the sign
bit of the 32-bit AArch32 NF/VF to line up with the 64-bit AArch64 NF/VF in 
memory.

If that's not what you mean... then I don't know what you mean.


r~