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[Qemu-devel] [PATCH 3/9] mips/kvm: Implement PRid CP0 register
From: |
James Hogan |
Subject: |
[Qemu-devel] [PATCH 3/9] mips/kvm: Implement PRid CP0 register |
Date: |
Wed, 11 Mar 2015 15:22:45 +0000 |
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
Signed-off-by: James Hogan <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Leon Alrae <address@hidden>
Cc: Aurelien Jarno <address@hidden>
---
target-mips/kvm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
index 2ec7a6588568..730c67e247d8 100644
--- a/target-mips/kvm.c
+++ b/target-mips/kvm.c
@@ -222,6 +222,7 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int
level)
#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
+#define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
@@ -521,6 +522,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int
level)
DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
ret = err;
}
+ err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
+ if (err < 0) {
+ DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err);
+ ret = err;
+ }
err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
&env->CP0_ErrorEPC);
if (err < 0) {
@@ -607,6 +613,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs)
DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
ret = err;
}
+ err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
+ if (err < 0) {
+ DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err);
+ ret = err;
+ }
err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
&env->CP0_ErrorEPC);
if (err < 0) {
--
2.0.5
- [Qemu-devel] [PATCH 0/9] mips/kvm: Support FPU & SIMD (MSA) in MIPS KVM guests, James Hogan, 2015/03/11
- [Qemu-devel] [PATCH 1/9] mips/kvm: Drop KVM_REG_MIPS_COUNT_* definitions, James Hogan, 2015/03/11
- [Qemu-devel] [PATCH 5/9] mips/kvm: Support unsigned KVM registers, James Hogan, 2015/03/11
- [Qemu-devel] [PATCH 3/9] mips/kvm: Implement PRid CP0 register,
James Hogan <=
- [Qemu-devel] [PATCH 9/9] mips/kvm: Support MSA in MIPS KVM guests, James Hogan, 2015/03/11
- [Qemu-devel] [PATCH 6/9] mips/kvm: Support signed 64-bit KVM registers, James Hogan, 2015/03/11
- [Qemu-devel] [PATCH 8/9] mips/kvm: Support FPU in MIPS KVM guests, James Hogan, 2015/03/11
- [Qemu-devel] [PATCH 2/9] mips/kvm: Remove a couple of noisy DPRINTFs, James Hogan, 2015/03/11
- [Qemu-devel] [PATCH 7/9] mips/kvm: Add FP & MSA register definitions, James Hogan, 2015/03/11
- [Qemu-devel] [PATCH 4/9] mips/kvm: Implement Config CP0 registers, James Hogan, 2015/03/11