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[Qemu-devel] [PATCH target-arm v3 10/15] char: cadence_uart: Split state
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v3 10/15] char: cadence_uart: Split state struct and type into header |
Date: |
Mon, 16 Mar 2015 05:12:21 -0700 |
To allow using the device with modern SoC programming conventions. The
state struct needs to be visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
changed since v1:
Fix /* Public */ comment spacing (Alistair review)
hw/char/cadence_uart.c | 29 +----------------------------
include/hw/char/cadence_uart.h | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 28 deletions(-)
create mode 100644 include/hw/char/cadence_uart.h
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 23f548d..4509e01 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -16,9 +16,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
-#include "hw/sysbus.h"
-#include "sysemu/char.h"
-#include "qemu/timer.h"
+#include "hw/char/cadence_uart.h"
#ifdef CADENCE_UART_ERR_DEBUG
#define DB_PRINT(...) do { \
@@ -85,8 +83,6 @@
#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
-#define CADENCE_UART_RX_FIFO_SIZE 16
-#define CADENCE_UART_TX_FIFO_SIZE 16
#define UART_INPUT_CLK 50000000
#define R_CR (0x00/4)
@@ -108,29 +104,6 @@
#define R_PWID (0x40/4)
#define R_TTRIG (0x44/4)
-#define CADENCE_UART_R_MAX (0x48/4)
-
-#define TYPE_CADENCE_UART "cadence_uart"
-#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
- TYPE_CADENCE_UART)
-
-typedef struct {
- /*< private >*/
- SysBusDevice parent_obj;
- /*< public >*/
-
- MemoryRegion iomem;
- uint32_t r[CADENCE_UART_R_MAX];
- uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
- uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
- uint32_t rx_wpos;
- uint32_t rx_count;
- uint32_t tx_count;
- uint64_t char_tx_time;
- CharDriverState *chr;
- qemu_irq irq;
- QEMUTimer *fifo_trigger_handle;
-} CadenceUARTState;
static void uart_update_status(CadenceUARTState *s)
{
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
new file mode 100644
index 0000000..3456d4c
--- /dev/null
+++ b/include/hw/char/cadence_uart.h
@@ -0,0 +1,35 @@
+#ifndef CADENCE_UART_H_
+
+#include "hw/sysbus.h"
+#include "sysemu/char.h"
+#include "qemu/timer.h"
+
+#define CADENCE_UART_RX_FIFO_SIZE 16
+#define CADENCE_UART_TX_FIFO_SIZE 16
+
+#define CADENCE_UART_R_MAX (0x48/4)
+
+#define TYPE_CADENCE_UART "cadence_uart"
+#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
+ TYPE_CADENCE_UART)
+
+typedef struct {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ uint32_t r[CADENCE_UART_R_MAX];
+ uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
+ uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
+ uint32_t rx_wpos;
+ uint32_t rx_count;
+ uint32_t tx_count;
+ uint64_t char_tx_time;
+ CharDriverState *chr;
+ qemu_irq irq;
+ QEMUTimer *fifo_trigger_handle;
+} CadenceUARTState;
+
+#define CADENCE_UART_H_
+#endif
--
2.3.1.2.g90df61e.dirty
- Re: [Qemu-devel] [PATCH target-arm v3 04/15] arm: xlnx-zynqmp: Add GIC, (continued)
[Qemu-devel] [PATCH target-arm v3 02/15] target-arm: cpu64: Add support for cortex-a53, Peter Crosthwaite, 2015/03/16
[Qemu-devel] [PATCH target-arm v3 03/15] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/03/16
[Qemu-devel] [PATCH target-arm v3 01/15] target-arm: cpu64: Factor out ARM cortex init, Peter Crosthwaite, 2015/03/16
[Qemu-devel] [PATCH target-arm v3 13/15] arm: xilinx-ep108: Add external RAM, Peter Crosthwaite, 2015/03/16
[Qemu-devel] [PATCH target-arm v3 06/15] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/03/16
[Qemu-devel] [PATCH target-arm v3 10/15] char: cadence_uart: Split state struct and type into header,
Peter Crosthwaite <=
[Qemu-devel] [PATCH target-arm v3 09/15] char: cadence_uart: Clean up variable names, Peter Crosthwaite, 2015/03/16
[Qemu-devel] [PATCH target-arm v3 12/15] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/03/16
[Qemu-devel] [PATCH target-arm v3 15/15] arm: xlnx-zynqmp: Add PSCI setup, Peter Crosthwaite, 2015/03/16