[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH target-arm v4 08/16] net: cadence_gem: Split state s
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v4 08/16] net: cadence_gem: Split state struct and type into header |
Date: |
Mon, 23 Mar 2015 04:05:15 -0700 |
To allow using the device with modern SoC programming conventions. The
state struct needs to be visible to embed the device in SoC containers.
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
changed since v1:
Fix /* Public */ comment spacing (Alistair review)
hw/net/cadence_gem.c | 43 +-------------------------------------
include/hw/net/cadence_gem.h | 49 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+), 42 deletions(-)
create mode 100644 include/hw/net/cadence_gem.h
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 5994306..dafe914 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -24,8 +24,7 @@
#include <zlib.h> /* For crc32 */
-#include "hw/sysbus.h"
-#include "net/net.h"
+#include "hw/net/cadence_gem.h"
#include "net/checksum.h"
#ifdef CADENCE_GEM_ERR_DEBUG
@@ -141,8 +140,6 @@
#define GEM_DESCONF6 (0x00000294/4)
#define GEM_DESCONF7 (0x00000298/4)
-#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
-
/*****************************************/
#define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
#define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
@@ -349,44 +346,6 @@ static inline void rx_desc_set_sar(unsigned *desc, int
sar_idx)
desc[1] |= R_DESC_1_RX_SAR_MATCH;
}
-#define TYPE_CADENCE_GEM "cadence_gem"
-#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
-
-typedef struct CadenceGEMState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- NICState *nic;
- NICConf conf;
- qemu_irq irq;
-
- /* GEM registers backing store */
- uint32_t regs[CADENCE_GEM_MAXREG];
- /* Mask of register bits which are write only */
- uint32_t regs_wo[CADENCE_GEM_MAXREG];
- /* Mask of register bits which are read only */
- uint32_t regs_ro[CADENCE_GEM_MAXREG];
- /* Mask of register bits which are clear on read */
- uint32_t regs_rtc[CADENCE_GEM_MAXREG];
- /* Mask of register bits which are write 1 to clear */
- uint32_t regs_w1c[CADENCE_GEM_MAXREG];
-
- /* PHY registers backing store */
- uint16_t phy_regs[32];
-
- uint8_t phy_loop; /* Are we in phy loopback? */
-
- /* The current DMA descriptor pointers */
- uint32_t rx_desc_addr;
- uint32_t tx_desc_addr;
-
- uint8_t can_rx_state; /* Debug only */
-
- unsigned rx_desc[2];
-
- bool sar_active[4];
-} CadenceGEMState;
-
/* The broadcast MAC address: 0xFFFFFFFFFFFF */
static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
new file mode 100644
index 0000000..12de820
--- /dev/null
+++ b/include/hw/net/cadence_gem.h
@@ -0,0 +1,49 @@
+#ifndef CADENCE_GEM_H_
+
+#define TYPE_CADENCE_GEM "cadence_gem"
+#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
+
+#include "net/net.h"
+#include "hw/sysbus.h"
+
+#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
+
+typedef struct CadenceGEMState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ NICState *nic;
+ NICConf conf;
+ qemu_irq irq;
+
+ /* GEM registers backing store */
+ uint32_t regs[CADENCE_GEM_MAXREG];
+ /* Mask of register bits which are write only */
+ uint32_t regs_wo[CADENCE_GEM_MAXREG];
+ /* Mask of register bits which are read only */
+ uint32_t regs_ro[CADENCE_GEM_MAXREG];
+ /* Mask of register bits which are clear on read */
+ uint32_t regs_rtc[CADENCE_GEM_MAXREG];
+ /* Mask of register bits which are write 1 to clear */
+ uint32_t regs_w1c[CADENCE_GEM_MAXREG];
+
+ /* PHY registers backing store */
+ uint16_t phy_regs[32];
+
+ uint8_t phy_loop; /* Are we in phy loopback? */
+
+ /* The current DMA descriptor pointers */
+ uint32_t rx_desc_addr;
+ uint32_t tx_desc_addr;
+
+ uint8_t can_rx_state; /* Debug only */
+
+ unsigned rx_desc[2];
+
+ bool sar_active[4];
+} CadenceGEMState;
+
+#define CADENCE_GEM_H_
+#endif
--
2.3.1.2.g90df61e.dirty
- [Qemu-devel] [PATCH target-arm v4 00/16] Next Generation Xilinx Zynq SoC, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 01/16] cpus: Don't kick un-realized cpus., Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 02/16] target-arm: cpu64: Factor out ARM cortex init, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 04/16] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 03/16] target-arm: cpu64: Add support for cortex-a53, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 05/16] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 08/16] net: cadence_gem: Split state struct and type into header,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v4 07/16] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 13/16] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 10/16] char: cadence_uart: Clean up variable names, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 14/16] arm: xilinx-ep108: Add external RAM, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 11/16] char: cadence_uart: Split state struct and type into header, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 15/16] arm: xilinx-ep108: Add bootloading, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 16/16] arm: xlnx-zynqmp: Add PSCI setup, Peter Crosthwaite, 2015/03/23