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[Qemu-devel] [PATCH target-arm v4 14/16] arm: xilinx-ep108: Add external
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v4 14/16] arm: xilinx-ep108: Add external RAM |
Date: |
Mon, 23 Mar 2015 04:05:18 -0700 |
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
changed since v1:
Add ram size clamps and warnings
hw/arm/xlnx-ep108.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
index 81704bb..6e89456 100644
--- a/hw/arm/xlnx-ep108.c
+++ b/hw/arm/xlnx-ep108.c
@@ -18,11 +18,16 @@
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
+#include "exec/address-spaces.h"
typedef struct XlnxEP108 {
XlnxZynqMPState soc;
+ MemoryRegion ddr_ram;
} XlnxEP108;
+/* Max 2GB RAM */
+#define EP108_MAX_RAM_SIZE 0x80000000ull
+
static void xlnx_ep108_init(MachineState *machine)
{
XlnxEP108 *s = g_new0(XlnxEP108, 1);
@@ -37,6 +42,22 @@ static void xlnx_ep108_init(MachineState *machine)
error_report("%s", error_get_pretty(err));
exit(1);
}
+
+ if (machine->ram_size > EP108_MAX_RAM_SIZE) {
+ error_report("WARNING: RAM size " RAM_ADDR_FMT " above max supported, "
+ "reduced to %llx", machine->ram_size, EP108_MAX_RAM_SIZE);
+ machine->ram_size = EP108_MAX_RAM_SIZE;
+ }
+
+ if (machine->ram_size <= 0x08000000) {
+ error_report("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108\n",
+ machine->ram_size);
+ }
+
+ memory_region_init_ram(&s->ddr_ram, NULL, "ddr-ram", machine->ram_size,
+ &error_abort);
+ vmstate_register_ram_global(&s->ddr_ram);
+ memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
}
static QEMUMachine xlnx_ep108_machine = {
--
2.3.1.2.g90df61e.dirty
- [Qemu-devel] [PATCH target-arm v4 04/16] arm: Introduce Xilinx ZynqMP SoC, (continued)
- [Qemu-devel] [PATCH target-arm v4 04/16] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 03/16] target-arm: cpu64: Add support for cortex-a53, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 05/16] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 08/16] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 07/16] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 13/16] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 10/16] char: cadence_uart: Clean up variable names, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 14/16] arm: xilinx-ep108: Add external RAM,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v4 11/16] char: cadence_uart: Split state struct and type into header, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 15/16] arm: xilinx-ep108: Add bootloading, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 16/16] arm: xlnx-zynqmp: Add PSCI setup, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 06/16] arm: xlnx-zynqmp: Connect CPU Timers to GIC, Peter Crosthwaite, 2015/03/23
- Re: [Qemu-devel] [PATCH target-arm v4 00/16] Next Generation Xilinx Zynq SoC, Alistair Francis, 2015/03/29