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Re: [Qemu-devel] [PATCH v5 1/6] target-arm: Store SPSR_EL1 state in bank
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v5 1/6] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc) |
Date: |
Tue, 24 Mar 2015 14:37:40 +0000 |
On 24 March 2015 at 14:32, Greg Bellows <address@hidden> wrote:
> On Mon, Mar 23, 2015 at 12:05 PM, Alex Bennée <address@hidden> wrote:
>> From: Peter Maydell <address@hidden>
>> @@ -523,7 +523,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
>> aarch64_save_sp(env, arm_current_el(env));
>> env->elr_el[new_el] = env->pc;
>> } else {
>> - env->banked_spsr[0] = cpsr_read(env);
>> + env->banked_spsr[aarch64_banked_spsr_index(new_el)] =
>> cpsr_read(env);
>
> Are the other banks (2-5) only used for KVM? It seems we go out of
> our way to manage this larger SPSR array then not use all of the slots
> in QEMU itself.
They're used in AArch32 (where they are the SPSR for various
32 bit modes). In AArch64 you can access those registers via
MSR/MRS (we probably haven't implemented those yet because they
are only accessible at EL2 and above) so hypervisors can do
worldswitches. But for exception entry and return (which is
what this code is) we only use SPSR_EL0/SPSR_EL1/SPSR_EL2/SPSR_EL3
which is a subset of the AArch32 SPSRs.
-- PMM
- [Qemu-devel] [PATCH v5 0/6] QEMU ARM64 Migration Fixes, Alex Bennée, 2015/03/23
- [Qemu-devel] [PATCH v5 6/6] target-arm: cpu.h document why env->spsr exists, Alex Bennée, 2015/03/23
- [Qemu-devel] [PATCH v5 1/6] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc), Alex Bennée, 2015/03/23
- [Qemu-devel] [PATCH v5 4/6] target-arm: kvm64 sync FP register state, Alex Bennée, 2015/03/23
- [Qemu-devel] [PATCH v5 5/6] target-arm: kvm64 fix save/restore of SPSR regs, Alex Bennée, 2015/03/23
- [Qemu-devel] [PATCH v5 2/6] target-arm: kvm: save/restore mp state, Alex Bennée, 2015/03/23
- [Qemu-devel] [PATCH v5 3/6] hw/intc: arm_gic_kvm.c restore config first, Alex Bennée, 2015/03/23