Re: [Qemu-devel] [PATCH 1/2] q35: implement SMRAM.D_LCK

[Michael S. Tsirkin]

On Tue, Apr 14, 2015 at 05:41:14PM +0200, Michael S. Tsirkin wrote:
> On Tue, Apr 14, 2015 at 03:12:39PM +0200, Gerd Hoffmann wrote:
> > Signed-off-by: Gerd Hoffmann <address@hidden>
> > ---
> >  hw/pci-host/q35.c | 17 ++++++++++++++++-
> >  1 file changed, 16 insertions(+), 1 deletion(-)
> > 
> > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> > index 79bab15..9227489 100644
> > --- a/hw/pci-host/q35.c
> > +++ b/hw/pci-host/q35.c
> > @@ -268,6 +268,20 @@ static void mch_update_smram(MCHPCIState *mch)
> >      PCIDevice *pd = PCI_DEVICE(mch);
> >      bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 
> > MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME);
> >  
> > +    /* implement SMRAM.D_LCK */
> > +    if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) {
> > +        pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN;
> > +
> > +        pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN;
> > +        pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_LCK;
> > +        pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= 
> > ~MCH_HOST_BRIDGE_SMRAM_G_SMRAME;
> > +        pd->wmask[MCH_HOST_BRIDGE_SMRAM] &= 
> > ~MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK;
> > +
> > +        pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] &= 
> > ~MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME;
> > +        pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] &= 
> > ~MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK;
> > +        pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] &= 
> > ~MCH_HOST_BRIDGE_ESMRAMC_T_EN;
> 
> 
> I'd prefer a single statement:
>       pd->wmask[MCH_HOST_BRIDGE_SMRAM] &=
>               ~(MCH_HOST_BRIDGE_SMRAM_D_OPEN | MCH_HOST_BRIDGE_SMRAM_D_LCK | 
> ... )
> 
> > +    }
> > +
> >      memory_region_transaction_begin();
> >  
> >      if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) {
> > @@ -297,7 +311,6 @@ static void mch_write_config(PCIDevice *d,
> >  {
> >      MCHPCIState *mch = MCH_PCI_DEVICE(d);
> >  
> > -    /* XXX: implement SMRAM.D_LOCK */
> >      pci_default_write_config(d, address, val, len);
> >  
> >      if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
> > @@ -351,6 +364,8 @@ static void mch_reset(DeviceState *qdev)
> >                   MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
> >  
> >      d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
> > +    d->wmask[MCH_HOST_BRIDGE_SMRAM] = 0xff;
> 
> Is this right? I see a bunch of reserved bits etc there.
> 
> 
> > +    d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = 0xff;

And this mask seems not to match the spec, either.

> Doesn't this mean we need to reset this register now?
> 
> >  
> >      mch_update(mch);
> >  }
> 
> Don't you also need to clear D_LCK?
> 
> > -- 
> > 1.8.3.1