Re: [Qemu-devel] [PATCH 2/7] target-mips: support Page Frame Number Extension field

[James Hogan]

On Tue, Apr 28, 2015 at 04:59:20PM +0100, Leon Alrae wrote:
> Hi James,
> 
> On 28/04/2015 14:35, James Hogan wrote:
> > 
> > 
> > On 28/04/15 13:41, Leon Alrae wrote:
> >> Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large
> >> physical address is not supported.
> >>
> >> Signed-off-by: Leon Alrae <address@hidden>
> >> ---
> >>  target-mips/op_helper.c | 32 ++++++++++++++++++++++++++------
> >>  1 file changed, 26 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> >> index c9a60bd..6bff927 100644
> >> --- a/target-mips/op_helper.c
> >> +++ b/target-mips/op_helper.c
> >> @@ -1825,6 +1825,16 @@ static void r4k_mips_tlb_flush_extra (CPUMIPSState 
> >> *env, int first)
> >>      }
> >>  }
> >>  
> >> +static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
> >> +{
> >> +#if defined(TARGET_MIPS64)
> >> +    return extract64(entrylo, 6, 54);
> >> +#else
> >> +    return extract64(entrylo, 6, 24) | /* PFN */
> >> +           (extract64(entrylo, 32, 32) << 24); /* PFNX */
> > 
> > Where does the 32,32 come from? The PRA I have seems to imply that PFNX
> > starts at bit 30 and goes up to bit 54.
> 
> This comes directly from MIPS32 PRA (I presume you are looking at MIPS64
> PRA).

Right, the MIPS32 64-bit representation is the same as what mfc0 and
mfhc0 would give you, and I see that the raw EntryLo representation in
QEMU already has XI/RI in different places depending on MIPS64/MIPS32,
i.e. following how each PRA represents the raw state differently.

I think I wasn't expecting that because 32-bit kernels can run on MIPS64
hardware using the same mfc0/mfhc0 instructions, so having a single
internal representation in QEMU seemed simpler & less fragile, since the
same source code needs to support both MIPS32 and MIPS64 anyway.

> Note that EntryLo.PFNX starts at bit 32 as there is 2-bit gap
> occupied by RI/XI (unlike MIPS64 where it starts at bit 30).

Well, from a programmer point of view mfc0 and mfhc0 with EntryLo behave
identically on both MIPS32 and MIPS64.

Thanks
James

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