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[Qemu-devel] [RFC 3/5] arm64: Add PMUSERENR_EL0 register
From: |
Christopher Covington |
Subject: |
[Qemu-devel] [RFC 3/5] arm64: Add PMUSERENR_EL0 register |
Date: |
Thu, 30 Apr 2015 14:14:25 -0400 |
The Linux kernel accesses this register early in its setup.
Signed-off-by: Christopher Covington <address@hidden>
---
target-arm/helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c9463cb..863cfd0 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -951,6 +951,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
.resetvalue = 0,
.writefn = pmuserenr_write, .raw_writefn = raw_write },
+ { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
+ .access = PL0_R | PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
+ .resetvalue = 0,
+ .writefn = pmuserenr_write, .raw_writefn = raw_write },
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 =
1,
.access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
--
1.9.1