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Re: [Qemu-devel] [PATCH v4 09/17] hw/intc/arm_gic: Implement Non-secure
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-devel] [PATCH v4 09/17] hw/intc/arm_gic: Implement Non-secure view of RPR |
Date: |
Tue, 5 May 2015 11:35:53 +1000 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Fri, May 01, 2015 at 06:50:35PM +0100, Peter Maydell wrote:
> From: Fabian Aggeler <address@hidden>
>
> For GICs with Security Extensions Non-secure reads have a restricted
> view on the current running priority.
>
> Signed-off-by: Fabian Aggeler <address@hidden>
> Signed-off-by: Greg Bellows <address@hidden>
> Message-id: address@hidden
> [PMM: make function static, minor comment tweak]
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
> ---
> hw/intc/arm_gic.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index 4aaaac2..e3bbe9e 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -286,6 +286,23 @@ static void gic_set_cpu_control(GICState *s, int cpu,
> uint32_t value,
> (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis");
> }
>
> +static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs
> attrs)
> +{
> + if (s->security_extn && !attrs.secure) {
> + if (s->running_priority[cpu] & 0x80) {
> + /* Running priority in upper half of range: return the Non-secure
> + * view of the priority.
> + */
> + return s->running_priority[cpu] << 1;
> + } else {
> + /* Running priority in lower half of range: RAZ */
> + return 0;
> + }
> + } else {
> + return s->running_priority[cpu];
> + }
> +}
> +
> void gic_complete_irq(GICState *s, int cpu, int irq)
> {
> int update = 0;
> @@ -817,7 +834,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int
> offset,
> *data = gic_acknowledge_irq(s, cpu);
> break;
> case 0x14: /* Running Priority */
> - *data = s->running_priority[cpu];
> + *data = gic_get_running_priority(s, cpu, attrs);
> break;
> case 0x18: /* Highest Pending Interrupt */
> *data = s->current_pending[cpu];
> --
> 1.9.1
>
- Re: [Qemu-devel] [PATCH v4 14/17] hw/intc/arm_gic: Add grouping support to gic_update(), (continued)
- [Qemu-devel] [PATCH v4 02/17] hw/intc/arm_gic: Add Security Extensions property, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 11/17] hw/intc/arm_gic: Handle grouping for GICC_HPPIR, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 10/17] hw/intc/arm_gic: Restrict priority view, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 08/17] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 09/17] hw/intc/arm_gic: Implement Non-secure view of RPR, Peter Maydell, 2015/05/01
- Re: [Qemu-devel] [PATCH v4 09/17] hw/intc/arm_gic: Implement Non-secure view of RPR,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v4 03/17] hw/intc/arm_gic: Switch to read/write callbacks with tx attributes, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 01/17] hw/intc/arm_gic: Create outbound FIQ lines, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 06/17] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 13/17] hw/intc/arm_gic: Change behavior of IAR writes, Peter Maydell, 2015/05/01
- [Qemu-devel] [PATCH v4 04/17] hw/intc/arm_gic: Add Interrupt Group Registers, Peter Maydell, 2015/05/01