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Re: [Qemu-devel] [PATCH target-arm v7 01/15] target-arm: cpu64: generali
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH target-arm v7 01/15] target-arm: cpu64: generalise name of A57 regs |
Date: |
Thu, 7 May 2015 14:52:28 +0100 |
On 6 May 2015 at 23:50, Peter Crosthwaite <address@hidden> wrote:
> Rename some A57 CP register variables in preparation for support for
> Cortex A53. Use "a57_a53" to describe the shareable features. Some of
> the CP15 registers (such as ACTLR) are specific to implementation, but
> we currently just RAZ them so continue with that as the policy for both
> A57 and A53 processors under a shared definition.
>
> Reviewed-by: Edgar E. Iglesias <address@hidden>
> Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- [Qemu-devel] [PATCH target-arm v7 05/15] arm: xlnx-zynqmp: Add GIC, (continued)
- [Qemu-devel] [PATCH target-arm v7 05/15] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 13/15] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 08/15] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 15/15] arm: xlnx-ep108: Add bootloading, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 11/15] char: cadence_uart: Split state struct and type into header, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 09/15] arm: xlnx-zynqmp: Add GEM support, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 14/15] arm: xlnx-ep108: Add external RAM, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 07/15] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 01/15] target-arm: cpu64: generalise name of A57 regs, Peter Crosthwaite, 2015/05/06
- Re: [Qemu-devel] [PATCH target-arm v7 01/15] target-arm: cpu64: generalise name of A57 regs,
Peter Maydell <=
- [Qemu-devel] [PATCH target-arm v7 10/15] char: cadence_uart: Clean up variable names, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 12/15] arm: xlnx-zynqmp: Add UART support, Peter Crosthwaite, 2015/05/06
- Re: [Qemu-devel] [PATCH target-arm v7 00/15] Next Generation Xilinx Zynq SoC, Peter Maydell, 2015/05/07