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[Qemu-devel] [PATCH target-arm v8 05/14] arm: xlnx-zynqmp: Connect CPU T
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v8 05/14] arm: xlnx-zynqmp: Connect CPU Timers to GIC |
Date: |
Thu, 7 May 2015 17:57:19 -0700 |
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Tested-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
changed since v4:
Use macro for GIC_INTERNAL
hw/arm/xlnx-zynqmp.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index a8ab7e7..1adaa46 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -16,10 +16,14 @@
*/
#include "hw/arm/xlnx-zynqmp.h"
+#include "hw/intc/arm_gic_common.h"
#include "exec/address-spaces.h"
#define GIC_NUM_SPI_INTR 128
+#define ARM_PHYS_TIMER_PPI 30
+#define ARM_VIRT_TIMER_PPI 27
+
#define GIC_BASE_ADDR 0xf9000000
#define GIC_DIST_ADDR 0xf9010000
#define GIC_CPU_ADDR 0xf9020000
@@ -34,6 +38,11 @@ static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] =
{
{ .region_index = 1, .address = GIC_CPU_ADDR, },
};
+static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
+{
+ return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
+}
+
static void xlnx_zynqmp_init(Object *obj)
{
XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
@@ -86,6 +95,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
}
for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
+ qemu_irq irq;
+
object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
if (i > 0) {
@@ -109,6 +120,12 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
+ arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
+ arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
}
}
--
2.4.0.3.ge0ccc3b.dirty
- [Qemu-devel] [PATCH target-arm v8 00/14] Next Generation Xilinx Zynq SoC, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 01/14] target-arm: cpu64: generalise name of A57 regs, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 02/14] target-arm: cpu64: Add support for Cortex-A53, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 03/14] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 04/14] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 05/14] arm: xlnx-zynqmp: Connect CPU Timers to GIC,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v8 06/14] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 07/14] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 08/14] arm: xlnx-zynqmp: Add GEM support, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 09/14] char: cadence_uart: Clean up variable names, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 10/14] char: cadence_uart: Split state struct and type into header, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 11/14] arm: xlnx-zynqmp: Add UART support, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 12/14] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 13/14] arm: xlnx-ep108: Add external RAM, Peter Crosthwaite, 2015/05/07
- [Qemu-devel] [PATCH target-arm v8 14/14] arm: xlnx-ep108: Add bootloading, Peter Crosthwaite, 2015/05/07
- Re: [Qemu-devel] [PATCH target-arm v8 00/14] Next Generation Xilinx Zynq SoC, Edgar E. Iglesias, 2015/05/14