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Re: [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation
From: |
alvise rigo |
Subject: |
Re: [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation |
Date: |
Mon, 11 May 2015 11:10:05 +0200 |
On Fri, May 8, 2015 at 8:29 PM, Emilio G. Cota <address@hidden> wrote:
> On Wed, May 06, 2015 at 17:38:02 +0200, Alvise Rigo wrote:
>> This patch series provides an infrastructure for atomic
>> instruction implementation in QEMU, paving the way for TCG multi-threading.
>> The adopted design does not rely on host atomic
>> instructions and is intended to propose a 'legacy' solution for
>> translating guest atomic instructions.
>
> Patch 2 doesn't apply to current master. I fixed the conflict manually
> and get a segfault before it boots:
>
> (gdb) bt
> #0 0x0000555555657b04 in test_bit (addr=<optimized out>, nr=<optimized out>)
> at /local/home/cota/src/qemu/include/qemu/bitops.h:119
> #1 cpu_physical_memory_excl_is_dirty (addr=18446744073709551615)
> at /local/home/cota/src/qemu/include/exec/ram_addr.h:214
> #2 tlb_set_page_with_attrs (cpu=<optimized out>, vaddr=<optimized out>,
> paddr=503316480, attrs=..., prot=<optimized out>, mmu_idx=3, size=1024)
> at /local/home/cota/src/qemu/cputlb.c:328
> #3 0x0000555555714c68 in arm_cpu_handle_mmu_fault (cs=0x555556334500,
> address=<optimized out>, access_type=0, mmu_idx=3)
> at /local/home/cota/src/qemu/target-arm/helper.c:5813
> #4 0x00005555557077b0 in tlb_fill (cs=0x555556334500, addr=<optimized out>,
> is_write=<optimized out>, mmu_idx=<optimized out>,
> retaddr=140737065132893)
> at /local/home/cota/src/qemu/target-arm/op_helper.c:69
> #5 0x000055555565939f in helper_le_ldul_mmu (env=0x55555633c750,
> addr=503316484, mmu_idx=3, retaddr=<optimized out>)
> at /local/home/cota/src/qemu/softmmu_template.h:192
> #6 0x00007fffe6c623db in code_gen_buffer ()
> #7 0x00005555556156ea in cpu_tb_exec (
> tb_ptr=0x7fffe6c62320 "A\213n\374\205\355\017\205\207",
> cpu=0x555556334500)
> at /local/home/cota/src/qemu/cpu-exec.c:199
> #8 cpu_arm_exec (env=0x55555633c750)
> at /local/home/cota/src/qemu/cpu-exec.c:519
> #9 0x000055555563c340 in tcg_cpu_exec (env=0x55555633c750)
> at /local/home/cota/src/qemu/cpus.c:1354
> #10 tcg_exec_all () at /local/home/cota/src/qemu/cpus.c:1387
> #11 qemu_tcg_cpu_thread_fn (arg=<optimized out>)
> at /local/home/cota/src/qemu/cpus.c:1032
> #12 0x00007ffff40dfe9a in start_thread (arg=0x7fffe4a45700)
> at pthread_create.c:308
> #13 0x00007ffff3e0d38d in clone ()
> at ../sysdeps/unix/sysv/linux/x86_64/clone.S:112
> #14 0x0000000000000000 in ?? ()
>
> It could be that my manual fix of the conflicts was wrong. What commit
> are your patches based on?
Hi,
the last commit was b8df9208f357d2b36e1b19634aea973618dc7ba8.
Regards,
alvise
>
> Thanks,
>
> Emilio
- [Qemu-devel] [RFC 5/5] target-arm: translate: implement qemu_ldlink and qemu_stcond ops, (continued)
- [Qemu-devel] [RFC 5/5] target-arm: translate: implement qemu_ldlink and qemu_stcond ops, Alvise Rigo, 2015/05/06
- Re: [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation, Paolo Bonzini, 2015/05/06
- Re: [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation, Mark Burton, 2015/05/06
- Re: [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation, Alex Bennée, 2015/05/08
- Re: [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation, Emilio G. Cota, 2015/05/08
- Re: [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation,
alvise rigo <=