Re: [Qemu-devel] Supporting multiple CPU AddressSpaces and memory transaction attributes

[Paolo Bonzini]

On 13/05/2015 13:21, Edgar E. Iglesias wrote:
> 
> It was not clear to me if CPUs should hook into the iommu notification
> system or if we should make the iommu notification code signal changes
> through AS change notifications.
> 
> The latter would be easy to get right I guess but we wouldn't be
> able to have any granularity in the flushing so performance could
> be better if the CPU somehow knows what parts have changed.

I think it's CPUs that should hook and flush their TLBs.

Paolo