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Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses
From: |
Leon Alrae |
Subject: |
Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA |
Date: |
Thu, 14 May 2015 09:51:29 +0100 |
User-agent: |
Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 |
On 13/05/2015 23:54, Maciej W. Rozycki wrote:
> On Wed, 13 May 2015, Richard Henderson wrote:
>
>>>> I believe the problem is that MSA vector register's size is 16-bytes
>>>> (this DATA_SIZE isn't supported in softmmu_template) and MSA load/store
>>>> is supposed to be atomic.
>>>
>>> Not really AFAICT. Here's what the specification says[1]:
>>>
>>> "The vector load instruction is atomic at the element level with no
>>> guaranteed ordering among elements, i.e. each element load is an atomic
>>> operation issued in no particular order with respect to the element's
>>> vector position."
>>>
>>> and[2]:
>>>
>>> "The vector store instruction is atomic at the element level with no
>>> guaranteed ordering among elements, i.e. each element store is an atomic
>>> operation issued in no particular order with respect to the element's
>>> vector position."
>>>
>>> so you only need to get atomic up to 8 bytes (with LD.D and ST.D, less
>>> with the narrower vector elements), and that looks supported to me.
>>
>> There's "atomic" in the transactional sense, and then there's "atomic" in the
>> visibility to other actors on the bus sense.
>>
>> Presumably Leon is talking about the first, wherein we must ensure all writes
>> to both pages must succeed. Which just means making sure that both pages are
>> present and writable before modifying any memory.
>
> I don't think we have. The specification is a bit unclear I must admit
> and it also defines the details of vector load and store operations as
> implementation dependent, so there's no further clarification.
This is specified in "MIPS Architecture For Programmers Volume I-A:
Introduction to the MIPS64 Architecture", Revision: 6.01, Imagination
Technologies, Document Number: MD00083, August 20, 2014, p.142:
"For example, a misaligned vector load instruction will never leave its
vector destination register half written, if part of a page split
succeeds and the other part takes an exception. It is either all done,
or not at all."
Leon
- [Qemu-devel] [PATCH v3 0/2] target-mips: Add support for misaligned accesses, Yongbok Kim, 2015/05/13
- [Qemu-devel] [PATCH v3 1/2] target-mips: Misaligned memory accesses for R6, Yongbok Kim, 2015/05/13
- [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Yongbok Kim, 2015/05/13
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Richard Henderson, 2015/05/13
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Maciej W. Rozycki, 2015/05/13
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Richard Henderson, 2015/05/13
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Leon Alrae, 2015/05/13
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Maciej W. Rozycki, 2015/05/13
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Richard Henderson, 2015/05/13
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Maciej W. Rozycki, 2015/05/13
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA,
Leon Alrae <=
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Maciej W. Rozycki, 2015/05/14
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Richard Henderson, 2015/05/13
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Yongbok Kim, 2015/05/14
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Yongbok Kim, 2015/05/14
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Richard Henderson, 2015/05/14
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Leon Alrae, 2015/05/14
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Richard Henderson, 2015/05/14
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Richard Henderson, 2015/05/14
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Leon Alrae, 2015/05/15
- Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA, Richard Henderson, 2015/05/15