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[Qemu-devel] [PATCH target-arm v9 11/14] arm: xlnx-zynqmp: Add UART supp
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v9 11/14] arm: xlnx-zynqmp: Add UART support |
Date: |
Thu, 14 May 2015 19:23:21 -0700 |
There are 2x Cadence UARTs in Zynq MP. Add them.
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
Changed since v4:
Remove ERR_PROP_CHECK_RETURN usage.
Changed since v1:
Fixed "UARTSs" typo
hw/arm/xlnx-zynqmp.c | 24 ++++++++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 3 +++
2 files changed, 27 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 456dea0..6b01965 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -36,6 +36,14 @@ static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
57, 59, 61, 63,
};
+static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
+ 0xFF000000, 0xFF010000,
+};
+
+static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
+ 21, 22,
+};
+
typedef struct XlnxZynqMPGICRegion {
int region_index;
uint32_t address;
@@ -70,6 +78,11 @@ static void xlnx_zynqmp_init(Object *obj)
object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
}
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
+ object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
+ qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
+ }
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -162,6 +175,17 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
gic_spi[gem_intr[i]]);
}
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
+ object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
+ if (err) {
+ error_propagate((errp), (err));
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
+ gic_spi[uart_intr[i]]);
+ }
}
static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index c6ccbd8..79c2b0b 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -21,6 +21,7 @@
#include "hw/arm/arm.h"
#include "hw/intc/arm_gic.h"
#include "hw/net/cadence_gem.h"
+#include "hw/char/cadence_uart.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
@@ -28,6 +29,7 @@
#define XLNX_ZYNQMP_NUM_CPUS 4
#define XLNX_ZYNQMP_NUM_GEMS 4
+#define XLNX_ZYNQMP_NUM_UARTS 2
#define XLNX_ZYNQMP_GIC_REGIONS 2
@@ -49,6 +51,7 @@ typedef struct XlnxZynqMPState {
GICState gic;
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
+ CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
} XlnxZynqMPState;
#define XLNX_ZYNQMP_H
--
2.4.0.3.ge0ccc3b.dirty
- [Qemu-devel] [PATCH target-arm v9 01/14] target-arm: cpu64: generalise name of A57 regs, (continued)
- [Qemu-devel] [PATCH target-arm v9 01/14] target-arm: cpu64: generalise name of A57 regs, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 02/14] target-arm: cpu64: Add support for Cortex-A53, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 03/14] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 04/14] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 05/14] arm: xlnx-zynqmp: Connect CPU Timers to GIC, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 06/14] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 07/14] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 08/14] arm: xlnx-zynqmp: Add GEM support, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 09/14] char: cadence_uart: Clean up variable names, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 10/14] char: cadence_uart: Split state struct and type into header, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 11/14] arm: xlnx-zynqmp: Add UART support,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v9 12/14] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 13/14] arm: xlnx-ep108: Add external RAM, Peter Crosthwaite, 2015/05/14
- [Qemu-devel] [PATCH target-arm v9 14/14] arm: xlnx-ep108: Add bootloading, Peter Crosthwaite, 2015/05/14
- Re: [Qemu-devel] [PATCH target-arm v9 00/14] Next Generation Xilinx Zynq SoC, Peter Maydell, 2015/05/18