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[Qemu-devel] [PATCH 1/3] target-tricore: fix OPC2_32_RR_DVINIT_HU having
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From: |
Bastian Koppelmann |
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Subject: |
[Qemu-devel] [PATCH 1/3] target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result |
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Date: |
Fri, 22 May 2015 12:15:56 +0200 |
If the argument r1 was the same as the extended result register r3+1, we would
overwrite r1 and then use it.
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 663b2a0..4b935fd 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6321,8 +6321,8 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
/* sv */
tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
/* write result */
- tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
+ tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
tcg_temp_free(temp);
tcg_temp_free(temp2);
tcg_temp_free(temp3);
--
2.4.1