Re: [Qemu-devel] [PATCH v6 3/4] cpu/apic: drop icc bus/bridge

[Andreas Färber]

Am 22.05.2015 um 18:56 schrieb Eduardo Habkost:
> On Fri, May 22, 2015 at 03:44:53PM +0800, Chen Fan wrote:
>>  static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
>> @@ -2801,8 +2793,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
>> **errp)
>>      }
>>
>>  #ifndef CONFIG_USER_ONLY
>> -    qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
>> -
>>      if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
>>          x86_cpu_apic_create(cpu, &local_err);
>>          if (local_err != NULL) {
>> diff --git a/vl.c b/vl.c
>> index 15bccc4..0c53053 100644
>> --- a/vl.c
>> +++ b/vl.c
>> @@ -1618,6 +1618,7 @@ void qemu_devices_reset(void)
>>      QTAILQ_FOREACH_SAFE(re, &reset_handlers, entry, nre) {
>>          re->func(re->opaque);
>>      }
>> +    reset_all_vcpus();
>>  }
> 
> What about all the other architectures and machines that may expect
> different reset ordering, and that already register their own CPU reset
> handlers?
> 
> If x86 has specific CPU reset ordering requirements, we should be able
> to ensure the expected ordering in x86-specific code (in pc.c?), not
> hardcode reset ordering for all machines.

+1

In particular pseries has special ordering requirements.

> (BTW, what was the motivation to move qemu_register_reset() from pc.c to
> target-i386/cpu.c? The only architectures that register reset handlers
> inside the CPU code are x86 and s390x, all others register reset
> handlers inside machine code.)

I don't remember the motivation, it was Anthony overturning my objection
against that exception from the rule though. If we can bring x86 or the
other targets back in line, feel free to make an RFC.
I still have an old branch with initial reset support for alpha and rth
had a patch to that effect, too.

Regards,
Andreas

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