Re: [Qemu-devel] [PATCH 12/14] target-arm: Move TB flags down to fill gap

[Edgar E. Iglesias]

On Tue, May 19, 2015 at 07:33:32PM +0100, Peter Maydell wrote:
> Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the
> bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and
> ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap.
> 
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Edgar E. Iglesias <address@hidden>


> ---
>  target-arm/cpu.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 647e0ba..dd7a90b 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -1761,13 +1761,13 @@ static inline bool arm_singlestep_active(CPUARMState 
> *env)
>  /* We store the bottom two bits of the CPAR as TB flags and handle
>   * checks on the other bits at runtime
>   */
> -#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20
> +#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
>  #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
>  /* Indicates whether cp register reads and writes by guest code should access
>   * the secure or nonsecure bank of banked registers; note that this is not
>   * the same thing as the current security state of the processor!
>   */
> -#define ARM_TBFLAG_NS_SHIFT         22
> +#define ARM_TBFLAG_NS_SHIFT         19
>  #define ARM_TBFLAG_NS_MASK          (1 << ARM_TBFLAG_NS_SHIFT)
>  
>  /* Bit usage when in AArch64 state: currently we have no A64 specific bits */
> -- 
> 1.9.1
>