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[Qemu-devel] [PULL 26/34] target-s390x: implement LPDFR and LNDFR instru
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 26/34] target-s390x: implement LPDFR and LNDFR instructions |
Date: |
Fri, 5 Jun 2015 01:41:56 +0200 |
From: Aurelien Jarno <address@hidden>
This complete the floating point support sign handling facility.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-s390x/insn-data.def | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index e638b0b..41b5f43 100644
--- a/target-s390x/insn-data.def
+++ b/target-s390x/insn-data.def
@@ -451,6 +451,7 @@
C(0xb301, LNEBR, RRE, Z, 0, e2, new, e1, nabsf32, f32)
C(0xb311, LNDBR, RRE, Z, 0, f2_o, f1, 0, nabsf64, f64)
C(0xb341, LNXBR, RRE, Z, 0, x2_o, x1, 0, nabsf128, f128)
+ C(0xb371, LNDFR, RRE, FPSSH, 0, f2_o, f1, 0, nabsf64, 0)
/* LOAD ON CONDITION */
C(0xb9f2, LOCR, RRF_c, LOC, r1, r2, new, r1_32, loc, 0)
C(0xb9e2, LOCGR, RRF_c, LOC, r1, r2, r1, 0, loc, 0)
@@ -464,6 +465,7 @@
C(0xb300, LPEBR, RRE, Z, 0, e2, new, e1, absf32, f32)
C(0xb310, LPDBR, RRE, Z, 0, f2_o, f1, 0, absf64, f64)
C(0xb340, LPXBR, RRE, Z, 0, x2_o, x1, 0, absf128, f128)
+ C(0xb370, LPDFR, RRE, FPSSH, 0, f2_o, f1, 0, absf64, 0)
/* LOAD REVERSED */
C(0xb91f, LRVR, RRE, Z, 0, r2_32u, new, r1_32, rev32, 0)
C(0xb90f, LRVGR, RRE, Z, 0, r2_o, r1, 0, rev64, 0)
--
1.7.12.4
- [Qemu-devel] [PULL 10/34] target-s390x: fix LOAD MULTIPLE instruction on page boundary, (continued)
- [Qemu-devel] [PULL 10/34] target-s390x: fix LOAD MULTIPLE instruction on page boundary, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 18/34] target-s390x: fix exception for invalid operation code, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 27/34] target-s390x: implement miscellaneous-instruction-extensions facility, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 23/34] target-s390x: implement LOAD FP INTEGER instructions, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 21/34] target-s390x: move STORE CLOCK FAST to the correct facility, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 32/34] target-s390x: use softmmu functions for mvcp/mvcs, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 19/34] target-s390x: fix CLGIT instruction, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 34/34] target-s390x: Only access allocated storage keys, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 17/34] target-s390x: implement LAY and LAEY instructions, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 29/34] target-s390x: implement high-word facility, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 26/34] target-s390x: implement LPDFR and LNDFR instructions,
Alexander Graf <=
- [Qemu-devel] [PULL 28/34] target-s390x: implement load-and-trap facility, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 31/34] target-s390x: support non current ASC in s390_cpu_handle_mmu_fault, Alexander Graf, 2015/06/04
- [Qemu-devel] [PULL 25/34] target-s390x: implement TRANSLATE EXTENDED instruction, Alexander Graf, 2015/06/04
- Re: [Qemu-devel] [PULL 00/34] s390 patch queue 2015-06-05, Peter Maydell, 2015/06/05