[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 42/62] target-i386: set G=1 in SMM big real mode sele
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 42/62] target-i386: set G=1 in SMM big real mode selectors |
Date: |
Fri, 5 Jun 2015 17:15:43 +0200 |
Because the limit field's bits 31:20 is 1, G should be 1.
VMX actually enforces this, let's do it for completeness
in QEMU as well.
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-i386/smm_helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c
index 6207c3a..5617a14 100644
--- a/target-i386/smm_helper.c
+++ b/target-i386/smm_helper.c
@@ -177,22 +177,22 @@ void do_smm_enter(X86CPU *cpu)
cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
- DESC_A_MASK);
+ DESC_G_MASK | DESC_A_MASK);
}
void helper_rsm(CPUX86State *env)
--
2.4.1
- [Qemu-devel] [PULL 31/62] migration: move dirty bitmap sync to ram_addr.h, (continued)
- [Qemu-devel] [PULL 31/62] migration: move dirty bitmap sync to ram_addr.h, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 33/62] memory: make cpu_physical_memory_sync_dirty_bitmap() fully atomic, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 32/62] memory: replace cpu_physical_memory_reset_dirty() with test-and-clear, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 34/62] memory: use mr->ram_addr in "is this RAM?" assertions, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 35/62] icount: implement a new icount_sleep mode toggleing real-time cpu sleep, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 36/62] icount: add sleep parameter to the icount option to set icount_sleep mode, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 37/62] icount: print a warning if there is no more deadline in sleep=no mode, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 38/62] target-i386: introduce cpu_get_mem_attrs, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 40/62] target-i386: Use correct memory attributes for ioport accesses, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 41/62] target-i386: mask NMIs on entry to SMM, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 42/62] target-i386: set G=1 in SMM big real mode selectors,
Paolo Bonzini <=
- [Qemu-devel] [PULL 43/62] target-i386: wake up processors that receive an SMI, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 44/62] pflash_cfi01: change big-endian property to BIT type, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 45/62] pflash_cfi01: change to new-style MMIO accessors, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 39/62] target-i386: Use correct memory attributes for memory accesses, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 46/62] pflash_cfi01: add secure property, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 47/62] vl: allow full-blown QemuOpts syntax for -global, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 48/62] qom: add object_property_add_const_link, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 49/62] vl: run "late" notifiers immediately, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 50/62] target-i386: create a separate AddressSpace for each CPU, Paolo Bonzini, 2015/06/05
- [Qemu-devel] [PULL 51/62] hw/i386: add a separate region that tracks the SMRAME bit, Paolo Bonzini, 2015/06/05