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Re: [Qemu-devel] [PATCH target-arm v1 6/9] target-arm: Implement PMSAv7
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH target-arm v1 6/9] target-arm: Implement PMSAv7 MPU |
Date: |
Wed, 10 Jun 2015 16:28:13 -0700 |
On Wed, Jun 10, 2015 at 3:21 PM, Peter Maydell <address@hidden> wrote:
> On 10 June 2015 at 23:17, Peter Crosthwaite
> <address@hidden> wrote:
>> On Tue, Jun 2, 2015 at 4:59 AM, Peter Maydell <address@hidden> wrote:
>>> On 1 June 2015 at 19:04, Peter Crosthwaite <address@hidden> wrote:
>>>> + switch (access_type) {
>>>> + case 0:
>>>> + return *prot & PAGE_READ ? 0 : 0x00D;
>>>> + case 1:
>>>> + return *prot & PAGE_WRITE ? 0 : 0x00D;
>>>> + case 2:
>>>> + return *prot & PAGE_EXEC ? 0 : 0x00D;
>>>
>>> This is
>>> if (!(*prot & (1 << access_type))) {
>>> return 0xD; /* Permission fault */
>>> } else {
>>> return 0;
>>> }
>>>
>>> isn't it?
>>>
>>
>> Yes but that assumes that access_type encoding is correlated to
>> PAGE_FOO masks so I didn't want this to break if one or the other was
>> re-encoded.
>
> We already do this in the lpae code path; I think it's safe.
>
Ok, doing it the quick way.
Regards,
Peter
- Re: [Qemu-devel] [PATCH target-arm v1 3/9] target-arm/helper.c: define MPUIR register, (continued)
[Qemu-devel] [PATCH target-arm v1 7/9] arm: r5: Implement dummy ATCM, BTCM and D-cache invalidate, Peter Crosthwaite, 2015/06/01
[Qemu-devel] [PATCH target-arm v1 8/9] arm: xlnx-zynqmp: Preface CPU variables with "A", Peter Crosthwaite, 2015/06/01
[Qemu-devel] [PATCH target-arm v1 9/9] arm: xlnx-zynqmp: Add 2xCortexR5 CPUs, Peter Crosthwaite, 2015/06/01