Re: [Qemu-devel] [PATCH v3 0/3] Support more than 8 MMU modes, speedup PPC by 10%

[Artyom Tarasenko]

Hi Paolo,

On Tue, May 5, 2015 at 9:18 AM, Paolo Bonzini <address@hidden> wrote:
> Patches 1 and 2 enable support from more than 8 MMU modes in TCG (patch
> 1 is in the targets, patch 2 is in cpu-defs.h).  The TLB size is reduced
> proportionally on targets where that is necessary.

This is a very promising approach. Would it also work on a large
numbers of MMU modes?
Particulary I wonder if it would work for SPARC, where 32-bit
processors have up to 65536 MMU contexts.

Regards,
Artyom

> Patch 3 uses the new support in the PPC target.
>
> Paolo
>
> v2->v3: - change i386 TCG_TARGET_TLB_DISPLACEMENT_BITS to 31 [rth]
>         - tweak comment in patch 2 to account for
>           offsetof(CPUArchState, tlb_table[mem_index][0].addend) [rth]
>
>
> Paolo Bonzini (3):
>   tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS
>   softmmu: support up to 12 MMU modes
>   target-ppc: use separate indices for various translation modes
>
>  include/exec/cpu-defs.h  |  34 +++++++++++++++-
>  include/exec/cpu_ldst.h  | 104 
> ++++++++++++++++++++++++++++++++++++++++++++---
>  target-ppc/cpu.h         |  12 +++---
>  target-ppc/excp_helper.c |   3 --
>  target-ppc/helper_regs.h |  15 ++++---
>  tcg/aarch64/tcg-target.h |   1 +
>  tcg/arm/tcg-target.h     |   1 +
>  tcg/i386/tcg-target.h    |   1 +
>  tcg/ia64/tcg-target.h    |   2 +
>  tcg/mips/tcg-target.h    |   1 +
>  tcg/ppc/tcg-target.h     |   1 +
>  tcg/s390/tcg-target.h    |   1 +
>  tcg/sparc/tcg-target.h   |   1 +
>  tcg/tci/tcg-target.h     |   1 +
>  14 files changed, 156 insertions(+), 22 deletions(-)
>
> --
> 2.3.5
>
>



-- 
Regards,
Artyom Tarasenko

SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu