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[Qemu-devel] [PATCH target-arm v2 08/13] arm: helper: rename get_phys_ad
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v2 08/13] arm: helper: rename get_phys_addr_mpu |
Date: |
Fri, 12 Jun 2015 12:10:44 -0700 |
This get_phys_addr is really for pmsav5. Rename it accordingly.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4a2965f..3f712a6 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5763,9 +5763,9 @@ do_fault:
return true;
}
-static bool get_phys_addr_mpu(CPUARMState *env, uint32_t address,
- int access_type, ARMMMUIdx mmu_idx,
- hwaddr *phys_ptr, int *prot, uint32_t *fsr)
+static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
+ int access_type, ARMMMUIdx mmu_idx,
+ hwaddr *phys_ptr, int *prot, uint32_t *fsr)
{
int n;
uint32_t mask;
@@ -5906,8 +5906,8 @@ static inline bool get_phys_addr(CPUARMState *env,
target_ulong address,
if (arm_feature(env, ARM_FEATURE_MPU)) {
*page_size = TARGET_PAGE_SIZE;
- return get_phys_addr_mpu(env, address, access_type, mmu_idx, phys_ptr,
- prot, fsr);
+ return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
+ phys_ptr, prot, fsr);
}
if (regime_using_lpae_format(env, mmu_idx)) {
--
2.4.3.3.g905f831
- [Qemu-devel] [PATCH target-arm v2 01/13] arm: Do not define TLBTR in PMSA systems, (continued)
- [Qemu-devel] [PATCH target-arm v2 01/13] arm: Do not define TLBTR in PMSA systems, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 02/13] arm: Don't add v7mp registers in MPU systems, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 03/13] arm: helper: Factor out CP regs common to [pv]msa, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 04/13] arm: Refactor get_phys_addr FSR return mechanism, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 05/13] arm: Implement uniprocessor with MP config, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 06/13] arm: Add has-mpu property, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 07/13] target-arm/helper.c: define MPUIR register, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 08/13] arm: helper: rename get_phys_addr_mpu,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v2 09/13] target-arm: Add registers for PMSAv7, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 11/13] target-arm: Add support for Cortex-R5, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 10/13] target-arm: Implement PMSAv7 MPU, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 12/13] arm: xlnx-zynqmp: Preface CPU variables with "apu", Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 13/13] arm: xlnx-zynqmp: Add 2xCortexR5 CPUs, Peter Crosthwaite, 2015/06/12
- Re: [Qemu-devel] [PATCH target-arm v2 00/13] ARM Cortex R5 Support, Peter Maydell, 2015/06/15