Re: [Qemu-devel] QEMU ARM SMP: IPI delivery delayed until next main loop event // how to improve IPI latency?

[Peter Maydell]

On 12 June 2015 at 17:38, Alex Züpke <address@hidden> wrote:
> Hi,
>
> I'm benchmarking some IPI (== inter-processor-interrupt) synchronization 
> stuff of my custom kernel on QEMU ARM (qemu-system-arm -M vexpress-a15 -smp 
> 2) and ran into the following problem: pending IPIs are delayed until the 
> QEMU main loop receives an event (for example the timer interrupt expires or 
> I press a key on the console).
>
> The following timing diagram tries to show this:
>
>   CPU #0                       CPU #1
>   ======                       ======
>   ... other stuff ...          WFI (wait for interrupt, like x86 "HLT")
>   send SGI in MPCore
>   polls for completeness
>                  <time passes ...>
>   polls ...
>                  <... and passes ...>
>   still polls ...
>                  <... and passes ...>
>   still polls ...
>                  <... and passes ...>
>
>
>                  <timer interrupt expires>
>                  <now QEMU switches to CPU #1>
>                                receives IPI
>                                signals completeness
>                                WFI
>                  <QEMU switches to CPU #0>
>   polling done
>   process timer interrupt
>   ...

Does your polling loop have a YIELD insn in it? We (and hardware)
can use that as a hint that you're busy-looping and we should
try doing something else. (QEMU doesn't implement that for A32/T32
yet, but we should; we already do on A64.)

-- PMM