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Re: [Qemu-devel] [RFC] Cortex-M different revisions


From: Liviu Ionescu
Subject: Re: [Qemu-devel] [RFC] Cortex-M different revisions
Date: Sun, 21 Jun 2015 17:42:59 +0300

> On 21 Jun 2015, at 17:09, Peter Maydell <address@hidden> wrote:
> 
> Non-buggy guest code should not care whether
> it is running on an r2p1 or an r2p0,

probably not, but code developed on an emulated r2 might very well break on a 
physical r0. 

> I think these should probably be cpu object properties, ...
> we get an accumulation
> of very similar CPUs, which we then don't actually emulate
> to a level of accuracy that would mean they make a difference
> to the guest.

I was considering to differentiate them only by cpu->midr, this should be easy.

later, when implementing accurate exception handling, I would need just to test 
the midr bits; I'm not sure it is worth to define properties for these things 
alone.

> Do you have real-world guest code that breaks?

yes, early M3 cores (for example the venerable STM32F1xx devices) have such 
issues that need to be addressed, usually at RTOS level, otherwise faults are 
raised.

I cannot confirm (because it was quite a while ago when I had to deal with 
these issues) that it is possible to write code that works an all versions 
without checking the actual version and acting differently.

my cortex-mcu object is now prepared for dealing with different versions, but 
for the moment I'll postpone extending the list of cpu's until really needed.


regards,

Liviu






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