Re: [Qemu-devel] [PATCH V2 3/7] introduce dpcd module.

[Peter Crosthwaite]

On Mon, Jun 15, 2015 at 8:15 AM,  <address@hidden> wrote:
> From: KONRAD Frederic <address@hidden>
>
> This introduces a DPCD modules. It wires on a aux-bus and can be accessed by

"module"

> driver to get lane-speed, etc.
>
> Signed-off-by: KONRAD Frederic <address@hidden>
> ---
>  hw/display/Makefile.objs |   1 +
>  hw/display/dpcd.c        | 151 
> +++++++++++++++++++++++++++++++++++++++++++++++
>  hw/display/dpcd.h        |  72 ++++++++++++++++++++++
>  3 files changed, 224 insertions(+)
>  create mode 100644 hw/display/dpcd.c
>  create mode 100644 hw/display/dpcd.h
>
> diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
> index 61c80f3..f75094f 100644
> --- a/hw/display/Makefile.objs
> +++ b/hw/display/Makefile.objs
> @@ -36,3 +36,4 @@ obj-$(CONFIG_VGA) += vga.o
>  common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
>
>  obj-$(CONFIG_VIRTIO) += virtio-gpu.o
> +obj-$(CONFIG_XLNX_ZYNQMP) += dpcd.o

Make a DPCD config and add to aarch64 defconfig.

> diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c
> new file mode 100644
> index 0000000..b4eeea7
> --- /dev/null
> +++ b/hw/display/dpcd.c
> @@ -0,0 +1,151 @@
> +/*
> + * dpcd.c
> + *
> + *  Copyright (C)2015 : GreenSocs Ltd

(C) 2015
(missing space)

> + *      http://www.greensocs.com/ , email: address@hidden
> + *
> + *  Developed by :
> + *  Frederic Konrad   <address@hidden>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option)any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +/*
> + * This is a simple AUX slave which emulates a connected screen.
> + */
> +
> +#include "hw/aux.h"
> +#include "dpcd.h"
> +
> +#ifndef DEBUG_DPCD
> +#define DEBUG_DPCD 0
> +#endif
> +
> +#define DPRINTF(fmt, ...) do {                                               
>   \
> +    if (DEBUG_DPCD) {                                                        
>   \
> +        qemu_log("dpcd: " fmt, ## __VA_ARGS__);                              
>   \
> +    }                                                                        
>   \
> +} while (0);
> +
> +#define DPCD_READABLE_AREA                      0x600
> +
> +struct DPCDState {

/*< public >*/

> +    AUXSlave parent_obj;
> +

/*< private >*/

> +    /*
> +     * The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF.
> +     */
> +    uint8_t dpcd_info[DPCD_READABLE_AREA];
> +
> +    MemoryRegion iomem;
> +};
> +
> +static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size)
> +{
> +    uint64_t ret;

make a uint8_t

> +    DPCDState *e = DPCD(opaque);
> +
> +    if (offset < DPCD_READABLE_AREA) {
> +        ret = e->dpcd_info[offset];
> +    } else {
> +        ret = 0;
> +    }
> +
> +    DPRINTF("read %u @0x%8.8lX\n", (uint8_t)ret, offset);

to avoid this cast, and just let the implicit cast on the return
handle it for you.

PRIx8
HWADDR_PRIx

> +    return ret;
> +}
> +
> +static void dpcd_write(void *opaque, hwaddr offset, uint64_t value,
> +                       unsigned size)
> +{
> +    DPCDState *e = DPCD(opaque);
> +
> +    DPRINTF("write %u @0x%8.8lX\n", (uint8_t)value, offset);
> +

PRIx8
HWADDR_PRIx

> +    if (offset < DPCD_READABLE_AREA) {
> +        e->dpcd_info[offset] = value;
> +    }

Should there be a else for a guest error?

> +}
> +
> +static const MemoryRegionOps aux_ops = {
> +    .read = dpcd_read,
> +    .write = dpcd_write,
> +    .valid = {
> +        .min_access_size = 1,
> +        .max_access_size = 1,
> +    },
> +    .impl = {
> +        .min_access_size = 1,
> +        .max_access_size = 1,
> +    },
> +};
> +
> +static void dpcd_reset(DeviceState *dev)
> +{
> +    DPCDState *s = DPCD(dev);

blank line.

> +    memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info));
> +
> +    s->dpcd_info[0x00] = DPCD_REV_1_0;
> +    s->dpcd_info[0x01] = DPCD_5_4GBPS;
> +    s->dpcd_info[0x02] = 0x1;
> +    s->dpcd_info[0x08] = DPCD_EDID_PRESENT;
> +    s->dpcd_info[0x09] = 0xFF;
> +
> +    /* CR DONE, CE DONE, SYMBOL LOCKED.. */
> +    s->dpcd_info[0x202] = 0x07;
> +    /* INTERLANE_ALIGN_DONE.. */
> +    s->dpcd_info[0x204] = 0x01;
> +    s->dpcd_info[0x205] = 0x01;

Magic numbers for both offsets and fields should be defined.

> +}
> +
> +static void dpcd_init(Object *obj)
> +{
> +    DPCDState *s = DPCD(obj);
> +
> +    memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
> +    aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
> +}
> +
> +static const VMStateDescription vmstate_dpcd = {
> +    .name = TYPE_DPCD,
> +    .version_id = 0,
> +    .minimum_version_id = 0,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINT8_ARRAY_V(dpcd_info, DPCDState, DPCD_READABLE_AREA, 0),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> +
> +static void dpcd_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);

blank line.


Regards,
Peter

> +    dc->reset = dpcd_reset;
> +    dc->vmsd = &vmstate_dpcd;
> +}
> +
> +static const TypeInfo dpcd_info = {
> +    .name          = TYPE_DPCD,
> +    .parent        = TYPE_AUX_SLAVE,
> +    .instance_size = sizeof(DPCDState),
> +    .class_init    = dpcd_class_init,
> +    .instance_init = dpcd_init,
> +};
> +
> +static void dpcd_register_types(void)
> +{
> +    type_register_static(&dpcd_info);
> +}
> +
> +type_init(dpcd_register_types)
> diff --git a/hw/display/dpcd.h b/hw/display/dpcd.h
> new file mode 100644
> index 0000000..57c393b
> --- /dev/null
> +++ b/hw/display/dpcd.h
> @@ -0,0 +1,72 @@
> +/*
> + * dpcd.h
> + *
> + *  Copyright (C)2015 : GreenSocs Ltd
> + *      http://www.greensocs.com/ , email: address@hidden
> + *
> + *  Developed by :
> + *  Frederic Konrad   <address@hidden>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option)any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#ifndef DPCD_H
> +#define DPCD_H
> +
> +typedef struct DPCDState DPCDState;
> +
> +#define TYPE_DPCD "dpcd"
> +#define DPCD(obj) OBJECT_CHECK(DPCDState, (obj), TYPE_DPCD)
> +
> +/* DCPD Revision. */
> +#define DPCD_REV_1_0                            0x10
> +#define DPCD_REV_1_1                            0x11
> +
> +/* DCPD Max Link Rate. */
> +#define DPCD_1_62GBPS                           0x06
> +#define DPCD_2_7GBPS                            0x0A
> +#define DPCD_5_4GBPS                            0x14
> +
> +/* DCPD Max down spread. */
> +#define DPCD_UP_TO_0_5                          0x01
> +#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING     0x40
> +
> +/* DCPD Downstream port type. */
> +#define DPCD_DISPLAY_PORT                       0x00
> +#define DPCD_ANALOG                             0x02
> +#define DPCD_DVI_HDMI                           0x04
> +#define DPCD_OTHER                              0x06
> +
> +/* DPCD Format conversion. */
> +#define DPCD_FORMAT_CONVERSION                  0x08
> +
> +/* Main link channel coding. */
> +#define DPCD_ANSI_8B_10B                        0x01
> +
> +/* Down stream port count. */
> +#define DPCD_OUI_SUPPORTED                      0x80
> +
> +/* Receiver port capability. */
> +#define DPCD_EDID_PRESENT                       0x02
> +#define DPCD_ASSOCIATED_TO_PRECEDING_PORT       0x04
> +
> +/* Down stream port capability. */
> +#define DPCD_CAP_DISPLAY_PORT                   0x000
> +#define DPCD_CAP_ANALOG_VGA                     0x001
> +#define DPCD_CAP_DVI                            0x002
> +#define DPCD_CAP_HDMI                           0x003
> +#define DPCD_CAP_OTHER                          0x100
> +
> +#endif /* !DPCD_H */
> --
> 1.9.0
>
>