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[Qemu-devel] [PATCH] target-mips: fix to clear MSACSR.Cause
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PATCH] target-mips: fix to clear MSACSR.Cause |
Date: |
Tue, 30 Jun 2015 15:44:28 +0100 |
MSACSR.Cause bits are needed to be cleared before a vector floating-point
instructions.
FEXDO.df, FEXUPL.df and FEXUPR.df were missed out.
Signed-off-by: Yongbok Kim <address@hidden>
---
target-mips/msa_helper.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-mips/msa_helper.c b/target-mips/msa_helper.c
index 26ffdc7..a1cb48f 100644
--- a/target-mips/msa_helper.c
+++ b/target-mips/msa_helper.c
@@ -2642,6 +2642,8 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
uint32_t i;
+ clear_msacsr_cause(env);
+
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
@@ -3192,6 +3194,8 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
uint32_t i;
+ clear_msacsr_cause(env);
+
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
@@ -3224,6 +3228,8 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
uint32_t i;
+ clear_msacsr_cause(env);
+
switch (df) {
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
--
1.7.5.4
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